[PATCH] D46679: [AArch64][SVE] Asm: Support for structured LD2, LD3 and LD4 (scalar+scalar) load instructions.

[Javed Absar via Phabricator via llvm-commits]

javed.absar added a comment.

Hi Florian.
I would then suggest adding the following to AArch64Schedule.td and then simply assigning the appropriate Scheds.
Much less work and neater doing it now when the instruction implementation is being done.

// Vector load and stores
def WriteSVE_VLD : SchedWrite;
def WriteSVE_VLD1 : SchedWrite;
def WriteSVE_VLD2 : SchedWrite;
def WriteSVE_VLD3 : SchedWrite;
def WriteSVE_VLD4 : SchedWrite;
def WriteSVE_VST : SchedWrite;
def WriteSVE_VST1 : SchedWrite;
def WriteSVE_VST2 : SchedWrite;
def WriteSVE_VST3 : SchedWrite;
def WriteSVE_VST4 : SchedWrite;

def ReadSVE_VLD : SchedRead;


https://reviews.llvm.org/D46679