[PATCH] D46647: [InstCombine] Teach SimplifyDemandedBits that udiv doesn't demand low dividend bits that are zero in the divisor

[Sanjoy Das via Phabricator via llvm-commits]

sanjoy added inline comments.


================
Comment at: lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp:556
+
+      APInt DemandedMaskIn =
+          APInt::getHighBitsSet(BitWidth, BitWidth - SA->countTrailingZeros());
----------------
bkramer wrote:
> sanjoy wrote:
> > Can we also propagate the demanded bits of the division result (in some form) into `DemandedMaskIn`?
> Maybe. This is hard for non-power of 2 divisors though and probably not worth the effort :|
I think demanded-bits should compose which means you can treat `a /u 12` as `(a >> 2) /u 3`.  Since in udiv input bit at index `i` can only affect output bits at index `i` and below (i.e. less significant) we should be able to left-smear the demanded bits demanded bits for `(a >> 2) /u 3` into the demanded bits for `(a >> 2)` and then apply the rule for `>>`.

For instance, if we demand bit only 5 for an `i8 a /u 12` == `(a >> 2) /u 3` then we can say:

 - We only need bits 5, 6, 7 and from `a >> 2`
 - Thus we only need bit 7 from `a`

I'd also be fine with a TODO here since it does seem complex.


Repository:
  rL LLVM

https://reviews.llvm.org/D46647