[llvm] r331790 - [Power9]Legalize and emit code for truncate and convert Quad-Precision to Word
Lei Huang via llvm-commits
llvm-commits at lists.llvm.org
Tue May 8 11:34:00 PDT 2018
Author: lei
Date: Tue May 8 11:34:00 2018
New Revision: 331790
URL: http://llvm.org/viewvc/llvm-project?rev=331790&view=rev
Log:
[Power9]Legalize and emit code for truncate and convert Quad-Precision to Word
Legalize and emit code for:
* xscvqpswz : VSX Scalar truncate & Convert Quad-Precision to Signed Word
* xscvqpuwz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Word
Differential Revision: https://reviews.llvm.org/D45635
Modified:
llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td
llvm/trunk/test/CodeGen/PowerPC/f128-truncateNconv.ll
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td?rev=331790&r1=331789&r2=331790&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td Tue May 8 11:34:00 2018
@@ -3173,6 +3173,10 @@ let AddedComplexity = 400, Predicates =
// Truncate & Convert QP -> (Un)Signed (D)Word.
def : Pat<(i64 (fp_to_sint f128:$src)), (i64 (MFVRD (XSCVQPSDZ $src)))>;
def : Pat<(i64 (fp_to_uint f128:$src)), (i64 (MFVRD (XSCVQPUDZ $src)))>;
+ def : Pat<(i32 (fp_to_sint f128:$src)),
+ (i32 (MFVSRWZ (COPY_TO_REGCLASS (XSCVQPSWZ $src), VFRC)))>;
+ def : Pat<(i32 (fp_to_uint f128:$src)),
+ (i32 (MFVSRWZ (COPY_TO_REGCLASS (XSCVQPUWZ $src), VFRC)))>;
// Instructions for fptosint (i64,i16,i8) feeding a store.
// The 8-byte version is repeated here due to availability of D-Form STXSD.
@@ -3185,6 +3189,9 @@ let AddedComplexity = 400, Predicates =
(STXSD (COPY_TO_REGCLASS (XSCVQPSDZ f128:$src), VFRC),
ixaddr:$dst)>;
def : Pat<(PPCstore_scal_int_from_vsr
+ (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), xoaddr:$dst, 4),
+ (STXSIWX (COPY_TO_REGCLASS (XSCVQPSWZ $src), VFRC), xoaddr:$dst)>;
+ def : Pat<(PPCstore_scal_int_from_vsr
(f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), xaddr:$dst, 8),
(STXSDX (XSCVDPSXDS f64:$src), xaddr:$dst)>;
def : Pat<(PPCstore_scal_int_from_vsr
@@ -3207,6 +3214,9 @@ let AddedComplexity = 400, Predicates =
(STXSD (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC),
ixaddr:$dst)>;
def : Pat<(PPCstore_scal_int_from_vsr
+ (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), xoaddr:$dst, 4),
+ (STXSIWX (COPY_TO_REGCLASS (XSCVQPUWZ $src), VFRC), xoaddr:$dst)>;
+ def : Pat<(PPCstore_scal_int_from_vsr
(f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), xaddr:$dst, 8),
(STXSDX (XSCVDPUXDS f64:$src), xaddr:$dst)>;
def : Pat<(PPCstore_scal_int_from_vsr
Modified: llvm/trunk/test/CodeGen/PowerPC/f128-truncateNconv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/f128-truncateNconv.ll?rev=331790&r1=331789&r2=331790&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/f128-truncateNconv.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/f128-truncateNconv.ll Tue May 8 11:34:00 2018
@@ -193,3 +193,155 @@ entry:
; CHECK-NEXT: stxsdx [[CONV]], 3, 4
; CHECK-NEXT: blr
}
+
+; Function Attrs: norecurse nounwind readonly
+define signext i32 @qpConv2sw(fp128* nocapture readonly %a) {
+entry:
+ %0 = load fp128, fp128* %a, align 16
+ %conv = fptosi fp128 %0 to i32
+ ret i32 %conv
+
+; CHECK-LABEL: qpConv2sw
+; CHECK: lxv [[REG:[0-9]+]], 0(3)
+; CHECK-NEXT: xscvqpswz [[CONV:[0-9]+]], [[REG]]
+; CHECK-NEXT: mfvsrwz [[REG2:[0-9]+]], [[CONV]]
+; CHECK-NEXT: extsw 3, [[REG2]]
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @qpConv2sw_02(i32* nocapture %res) {
+entry:
+ %0 = load fp128, fp128* getelementptr inbounds
+ ([4 x fp128], [4 x fp128]* @f128Array, i64 0,
+ i64 2), align 16
+ %conv = fptosi fp128 %0 to i32
+ store i32 %conv, i32* %res, align 4
+ ret void
+
+; CHECK-LABEL: qpConv2sw_02
+; CHECK: addis [[REG0:[0-9]+]], 2, .LC0 at toc@ha
+; CHECK: ld [[REG0]], .LC0 at toc@l([[REG0]])
+; CHECK: lxv [[REG:[0-9]+]], 32([[REG0]])
+; CHECK-NEXT: xscvqpswz [[CONV:[0-9]+]], [[REG]]
+; CHECK-NEXT: stxsiwx [[CONV]], 0, 3
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readonly
+define signext i32 @qpConv2sw_03(fp128* nocapture readonly %a) {
+entry:
+ %0 = load fp128, fp128* %a, align 16
+ %1 = load fp128, fp128* getelementptr inbounds
+ ([4 x fp128], [4 x fp128]* @f128Array, i64 0,
+ i64 1), align 16
+ %add = fadd fp128 %0, %1
+ %conv = fptosi fp128 %add to i32
+ ret i32 %conv
+
+; CHECK-LABEL: qpConv2sw_03
+; CHECK: addis [[REG0:[0-9]+]], 2, .LC0 at toc@ha
+; CHECK-DAG: ld [[REG0]], .LC0 at toc@l([[REG0]])
+; CHECK-DAG: lxv [[REG1:[0-9]+]], 16([[REG0]])
+; CHECK-DAG: lxv [[REG:[0-9]+]], 0(3)
+; CHECK-NEXT: xsaddqp [[ADD:[0-9]+]], [[REG]], [[REG1]]
+; CHECK-NEXT: xscvqpswz [[CONV:[0-9]+]], [[ADD]]
+; CHECK-NEXT: mfvsrwz [[REG2:[0-9]+]], [[CONV]]
+; CHECK-NEXT: extsw 3, [[REG2]]
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @qpConv2sw_04(fp128* nocapture readonly %a,
+ fp128* nocapture readonly %b, i32* nocapture %res) {
+entry:
+ %0 = load fp128, fp128* %a, align 16
+ %1 = load fp128, fp128* %b, align 16
+ %add = fadd fp128 %0, %1
+ %conv = fptosi fp128 %add to i32
+ store i32 %conv, i32* %res, align 4
+ ret void
+
+; CHECK-LABEL: qpConv2sw_04
+; CHECK-DAG: lxv [[REG1:[0-9]+]], 0(4)
+; CHECK-DAG: lxv [[REG:[0-9]+]], 0(3)
+; CHECK-NEXT: xsaddqp [[ADD:[0-9]+]], [[REG]], [[REG1]]
+; CHECK-NEXT: xscvqpswz [[CONV:[0-9]+]], [[ADD]]
+; CHECK-NEXT: stxsiwx [[CONV]], 0, 5
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind readonly
+define zeroext i32 @qpConv2uw(fp128* nocapture readonly %a) {
+entry:
+ %0 = load fp128, fp128* %a, align 16
+ %conv = fptoui fp128 %0 to i32
+ ret i32 %conv
+
+; CHECK-LABEL: qpConv2uw
+; CHECK: lxv [[REG:[0-9]+]], 0(3)
+; CHECK-NEXT: xscvqpuwz [[CONV:[0-9]+]], [[ADD]]
+; CHECK-NEXT: mfvsrwz 3, [[CONV]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @qpConv2uw_02(i32* nocapture %res) {
+entry:
+ %0 = load fp128, fp128* getelementptr inbounds
+ ([4 x fp128], [4 x fp128]* @f128Array, i64 0,
+ i64 2), align 16
+ %conv = fptoui fp128 %0 to i32
+ store i32 %conv, i32* %res, align 4
+ ret void
+
+; CHECK-LABEL: qpConv2uw_02
+; CHECK: addis [[REG0:[0-9]+]], 2, .LC0 at toc@ha
+; CHECK: ld [[REG0]], .LC0 at toc@l([[REG0]])
+; CHECK: lxv [[REG:[0-9]+]], 32([[REG0]])
+; CHECK-NEXT: xscvqpuwz [[CONV:[0-9]+]], [[ADD]]
+; CHECK-NEXT: stxsiwx [[CONV]], 0, 3
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind readonly
+define zeroext i32 @qpConv2uw_03(fp128* nocapture readonly %a) {
+entry:
+ %0 = load fp128, fp128* %a, align 16
+ %1 = load fp128, fp128* getelementptr inbounds
+ ([4 x fp128], [4 x fp128]* @f128Array, i64 0,
+ i64 1), align 16
+ %add = fadd fp128 %0, %1
+ %conv = fptoui fp128 %add to i32
+ ret i32 %conv
+
+; CHECK-LABEL: qpConv2uw_03
+; CHECK: addis [[REG0:[0-9]+]], 2, .LC0 at toc@ha
+; CHECK-DAG: ld [[REG0]], .LC0 at toc@l([[REG0]])
+; CHECK-DAG: lxv [[REG1:[0-9]+]], 16([[REG0]])
+; CHECK-DAG: lxv [[REG:[0-9]+]], 0(3)
+; CHECK-NEXT: xsaddqp [[ADD:[0-9]+]], [[REG]], [[REG1]]
+; CHECK-NEXT: xscvqpuwz [[CONV:[0-9]+]], [[ADD]]
+; CHECK-NEXT: mfvsrwz 3, [[CONV]]
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @qpConv2uw_04(fp128* nocapture readonly %a,
+ fp128* nocapture readonly %b, i32* nocapture %res) {
+entry:
+ %0 = load fp128, fp128* %a, align 16
+ %1 = load fp128, fp128* %b, align 16
+ %add = fadd fp128 %0, %1
+ %conv = fptoui fp128 %add to i32
+ store i32 %conv, i32* %res, align 4
+ ret void
+
+; CHECK-LABEL: qpConv2uw_04
+; CHECK-DAG: lxv [[REG1:[0-9]+]], 0(4)
+; CHECK-DAG: lxv [[REG:[0-9]+]], 0(3)
+; CHECK-NEXT: xsaddqp [[ADD:[0-9]+]], [[REG]], [[REG1]]
+; CHECK-NEXT: xscvqpuwz [[CONV:[0-9]+]], [[ADD]]
+; CHECK-NEXT: stxsiwx [[CONV]], 0, 5
+; CHECK: blr
+}
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