[llvm] r331757 - [X86] Add SchedWriteFTest/SchedWriteVecTest TEST scheduler classes
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Tue May 8 03:28:03 PDT 2018
Author: rksimon
Date: Tue May 8 03:28:03 2018
New Revision: 331757
URL: http://llvm.org/viewvc/llvm-project?rev=331757&view=rev
Log:
[X86] Add SchedWriteFTest/SchedWriteVecTest TEST scheduler classes
Split off from SchedWriteVecLogic to remove InstRW overrides.
Modified:
llvm/trunk/lib/Target/X86/X86InstrSSE.td
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
llvm/trunk/lib/Target/X86/X86Schedule.td
llvm/trunk/lib/Target/X86/X86ScheduleAtom.td
llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
llvm/trunk/lib/Target/X86/X86ScheduleSLM.td
llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=331757&r1=331756&r2=331757&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue May 8 03:28:03 2018
@@ -5694,21 +5694,21 @@ let Defs = [EFLAGS], Predicates = [HasAV
def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
"vptest\t{$src2, $src1|$src1, $src2}",
[(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
- Sched<[SchedWriteVecLogic.XMM]>, VEX, VEX_WIG;
+ Sched<[SchedWriteVecTest.XMM]>, VEX, VEX_WIG;
def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
"vptest\t{$src2, $src1|$src1, $src2}",
[(set EFLAGS,(X86ptest VR128:$src1, (loadv2i64 addr:$src2)))]>,
- Sched<[SchedWriteVecLogic.XMM.Folded, ReadAfterLd]>,
+ Sched<[SchedWriteVecTest.XMM.Folded, ReadAfterLd]>,
VEX, VEX_WIG;
def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
"vptest\t{$src2, $src1|$src1, $src2}",
[(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
- Sched<[SchedWriteVecLogic.YMM]>, VEX, VEX_L, VEX_WIG;
+ Sched<[SchedWriteVecTest.YMM]>, VEX, VEX_L, VEX_WIG;
def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
"vptest\t{$src2, $src1|$src1, $src2}",
[(set EFLAGS,(X86ptest VR256:$src1, (loadv4i64 addr:$src2)))]>,
- Sched<[SchedWriteVecLogic.YMM.Folded, ReadAfterLd]>,
+ Sched<[SchedWriteVecTest.YMM.Folded, ReadAfterLd]>,
VEX, VEX_L, VEX_WIG;
}
@@ -5716,11 +5716,11 @@ let Defs = [EFLAGS] in {
def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
"ptest\t{$src2, $src1|$src1, $src2}",
[(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
- Sched<[SchedWriteVecLogic.XMM]>;
+ Sched<[SchedWriteVecTest.XMM]>;
def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
"ptest\t{$src2, $src1|$src1, $src2}",
[(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
- Sched<[SchedWriteVecLogic.XMM.Folded, ReadAfterLd]>;
+ Sched<[SchedWriteVecTest.XMM.Folded, ReadAfterLd]>;
}
// The bit test instructions below are AVX only
@@ -5740,15 +5740,15 @@ multiclass avx_bittest<bits<8> opc, stri
let Defs = [EFLAGS], Predicates = [HasAVX] in {
let ExeDomain = SSEPackedSingle in {
defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, loadv4f32, v4f32,
- SchedWriteVecLogic.XMM>;
+ SchedWriteFTest.XMM>;
defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, loadv8f32, v8f32,
- SchedWriteVecLogic.YMM>, VEX_L;
+ SchedWriteFTest.YMM>, VEX_L;
}
let ExeDomain = SSEPackedDouble in {
defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, loadv2f64, v2f64,
- SchedWriteVecLogic.XMM>;
+ SchedWriteFTest.XMM>;
defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, loadv4f64, v4f64,
- SchedWriteVecLogic.YMM>, VEX_L;
+ SchedWriteFTest.YMM>, VEX_L;
}
}
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=331757&r1=331756&r2=331757&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Tue May 8 03:28:03 2018
@@ -220,6 +220,8 @@ defm : X86WriteRes<WriteFRndLd, [BWPort
defm : X86WriteRes<WriteFRndYLd, [BWPort1,BWPort23], 12, [2,1], 3>;
defm : BWWriteResPair<WriteFLogic, [BWPort5], 1, [1], 1, 5>; // Floating point and/or/xor logicals.
defm : BWWriteResPair<WriteFLogicY, [BWPort5], 1, [1], 1, 6>; // Floating point and/or/xor logicals (YMM/ZMM).
+defm : BWWriteResPair<WriteFTest, [BWPort0], 1, [1], 1, 5>; // Floating point TEST instructions.
+defm : BWWriteResPair<WriteFTestY, [BWPort0], 1, [1], 1, 6>; // Floating point TEST instructions (YMM/ZMM).
defm : BWWriteResPair<WriteFShuffle, [BWPort5], 1, [1], 1, 5>; // Floating point vector shuffles.
defm : BWWriteResPair<WriteFShuffleY, [BWPort5], 1, [1], 1, 6>; // Floating point vector shuffles (YMM/ZMM).
defm : BWWriteResPair<WriteFVarShuffle, [BWPort5], 1, [1], 1, 5>; // Floating point vector variable shuffles.
@@ -248,6 +250,8 @@ defm : BWWriteResPair<WriteVecALU, [BW
defm : BWWriteResPair<WriteVecALUY, [BWPort15], 1, [1], 1, 6>; // Vector integer ALU op, no logicals (YMM/ZMM).
defm : BWWriteResPair<WriteVecLogic, [BWPort015], 1, [1], 1, 5>; // Vector integer and/or/xor.
defm : BWWriteResPair<WriteVecLogicY,[BWPort015], 1, [1], 1, 6>; // Vector integer and/or/xor (YMM/ZMM).
+defm : BWWriteResPair<WriteVecTest, [BWPort0,BWPort5], 2, [1,1], 2, 5>; // Vector integer TEST instructions.
+defm : BWWriteResPair<WriteVecTestY, [BWPort0,BWPort5], 4, [1,1], 2, 6>; // Vector integer TEST instructions (YMM/ZMM).
defm : BWWriteResPair<WriteVecIMul, [BWPort0], 5, [1], 1, 5>; // Vector integer multiply.
defm : BWWriteResPair<WriteVecIMulX, [BWPort0], 5, [1], 1, 5>; // Vector integer multiply.
defm : BWWriteResPair<WriteVecIMulY, [BWPort0], 5, [1], 1, 6>; // Vector integer multiply.
@@ -440,9 +444,7 @@ def: InstRW<[BWWriteResGroup1], (instreg
"(V?)MOVPDI2DIrr",
"(V?)MOVPQIto64rr",
"VPSLLVQ(Y?)rr",
- "VPSRLVQ(Y?)rr",
- "VTESTPD(Y?)rr",
- "VTESTPS(Y?)rr")>;
+ "VPSRLVQ(Y?)rr")>;
def BWWriteResGroup2 : SchedWriteRes<[BWPort1]> {
let Latency = 1;
@@ -601,8 +603,7 @@ def BWWriteResGroup15 : SchedWriteRes<[B
}
def: InstRW<[BWWriteResGroup15], (instregex "VCVTPH2PS(Y?)rr",
"(V?)CVTPS2PDrr",
- "(V?)CVTSS2SDrr",
- "(V?)PTESTrr")>;
+ "(V?)CVTSS2SDrr")>;
def BWWriteResGroup16 : SchedWriteRes<[BWPort6,BWPort0156]> {
let Latency = 2;
@@ -784,8 +785,7 @@ def BWWriteResGroup40 : SchedWriteRes<[B
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[BWWriteResGroup40], (instregex "VCVTPS2PDYrr",
- "VPTESTYrr")>;
+def: InstRW<[BWWriteResGroup40], (instregex "VCVTPS2PDYrr")>;
def BWWriteResGroup41 : SchedWriteRes<[BWPort0,BWPort0156]> {
let Latency = 4;
@@ -970,9 +970,7 @@ def: InstRW<[BWWriteResGroup59], (instre
"(V?)CVTPS2PDrm",
"(V?)CVTSS2SDrm",
"VPSLLVQrm",
- "VPSRLVQrm",
- "VTESTPDrm",
- "VTESTPSrm")>;
+ "VPSRLVQrm")>;
def BWWriteResGroup60 : SchedWriteRes<[BWPort1,BWPort5]> {
let Latency = 6;
@@ -1083,9 +1081,7 @@ def BWWriteResGroup73 : SchedWriteRes<[B
let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup73], (instregex "VPSLLVQYrm",
- "VPSRLVQYrm",
- "VTESTPDYrm",
- "VTESTPSYrm")>;
+ "VPSRLVQYrm")>;
def BWWriteResGroup74 : SchedWriteRes<[BWPort1,BWPort23]> {
let Latency = 7;
@@ -1125,13 +1121,6 @@ def BWWriteResGroup80 : SchedWriteRes<[B
def: InstRW<[BWWriteResGroup80], (instrs LEAVE, LEAVE64,
SCASB, SCASL, SCASQ, SCASW)>;
-def BWWriteResGroup81 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
- let Latency = 7;
- let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
-}
-def: InstRW<[BWWriteResGroup81], (instregex "(V?)PTESTrm")>;
-
def BWWriteResGroup82 : SchedWriteRes<[BWPort0,BWPort01,BWPort23]> {
let Latency = 7;
let NumMicroOps = 3;
@@ -1383,13 +1372,6 @@ def: InstRW<[BWWriteResGroup117], (instr
"FICOMP16m",
"FICOMP32m")>;
-def BWWriteResGroup118 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
- let Latency = 10;
- let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
-}
-def: InstRW<[BWWriteResGroup118], (instregex "VPTESTYrm")>;
-
def BWWriteResGroup120 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
let Latency = 10;
let NumMicroOps = 4;
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=331757&r1=331756&r2=331757&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Tue May 8 03:28:03 2018
@@ -215,6 +215,8 @@ defm : X86WriteRes<WriteFRndLd, [HWPort
defm : X86WriteRes<WriteFRndYLd, [HWPort1,HWPort23], 13, [2,1], 3>;
defm : HWWriteResPair<WriteFLogic, [HWPort5], 1, [1], 1, 6>;
defm : HWWriteResPair<WriteFLogicY, [HWPort5], 1, [1], 1, 7>;
+defm : HWWriteResPair<WriteFTest, [HWPort0], 1, [1], 1, 6>;
+defm : HWWriteResPair<WriteFTestY, [HWPort0], 1, [1], 1, 7>;
defm : HWWriteResPair<WriteFShuffle, [HWPort5], 1, [1], 1, 6>;
defm : HWWriteResPair<WriteFShuffleY, [HWPort5], 1, [1], 1, 7>;
defm : HWWriteResPair<WriteFVarShuffle, [HWPort5], 1, [1], 1, 6>;
@@ -239,6 +241,8 @@ def : WriteRes<WriteVecMove, [HW
defm : HWWriteResPair<WriteVecLogic, [HWPort015], 1, [1], 1, 6>;
defm : HWWriteResPair<WriteVecLogicY,[HWPort015], 1, [1], 1, 7>;
+defm : HWWriteResPair<WriteVecTest, [HWPort0,HWPort5], 2, [1,1], 2, 6>;
+defm : HWWriteResPair<WriteVecTestY, [HWPort0,HWPort5], 4, [1,1], 2, 7>;
defm : HWWriteResPair<WriteVecALU, [HWPort15], 1, [1], 1, 6>;
defm : HWWriteResPair<WriteVecALUY, [HWPort15], 1, [1], 1, 7>;
defm : HWWriteResPair<WriteVecIMul, [HWPort0], 5, [1], 1, 5>;
@@ -771,9 +775,7 @@ def: InstRW<[HWWriteResGroup2], (instreg
"(V?)MOVPDI2DIrr",
"(V?)MOVPQIto64rr",
"VPSLLVQ(Y?)rr",
- "VPSRLVQ(Y?)rr",
- "VTESTPD(Y?)rr",
- "VTESTPS(Y?)rr")>;
+ "VPSRLVQ(Y?)rr")>;
def HWWriteResGroup3 : SchedWriteRes<[HWPort1]> {
let Latency = 1;
@@ -876,9 +878,7 @@ def HWWriteResGroup11_1 : SchedWriteRes<
def: InstRW<[HWWriteResGroup11_1], (instregex "VCVTPH2PSYrm",
"(V?)CVTSS2SDrm",
"VPSLLVQrm",
- "VPSRLVQrm",
- "VTESTPDrm",
- "VTESTPSrm")>;
+ "VPSRLVQrm")>;
def HWWriteResGroup11_2 : SchedWriteRes<[HWPort0,HWPort23]> {
let Latency = 8;
@@ -886,9 +886,7 @@ def HWWriteResGroup11_2 : SchedWriteRes<
let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup11_2], (instregex "VPSLLVQYrm",
- "VPSRLVQYrm",
- "VTESTPDYrm",
- "VTESTPSYrm")>;
+ "VPSRLVQYrm")>;
def HWWriteResGroup12 : SchedWriteRes<[HWPort1,HWPort23]> {
let Latency = 8;
@@ -1114,8 +1112,7 @@ def HWWriteResGroup31 : SchedWriteRes<[H
def: InstRW<[HWWriteResGroup31], (instregex "VCVTPH2PSYrr",
"VCVTPH2PSrr",
"(V?)CVTPS2PDrr",
- "(V?)CVTSS2SDrr",
- "(V?)PTESTrr")>;
+ "(V?)CVTSS2SDrr")>;
def HWWriteResGroup32 : SchedWriteRes<[HWPort6,HWPort0156]> {
let Latency = 2;
@@ -1196,13 +1193,6 @@ def HWWriteResGroup37 : SchedWriteRes<[H
def: InstRW<[HWWriteResGroup37], (instrs LEAVE, LEAVE64,
SCASB, SCASL, SCASQ, SCASW)>;
-def HWWriteResGroup38 : SchedWriteRes<[HWPort0,HWPort5,HWPort23]> {
- let Latency = 8;
- let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
-}
-def: InstRW<[HWWriteResGroup38], (instregex "(V?)PTESTrm")>;
-
def HWWriteResGroup39 : SchedWriteRes<[HWPort0,HWPort01,HWPort23]> {
let Latency = 7;
let NumMicroOps = 3;
@@ -1457,8 +1447,7 @@ def HWWriteResGroup71 : SchedWriteRes<[H
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[HWWriteResGroup71], (instregex "VCVTPS2PDYrr",
- "VPTESTYrr")>;
+def: InstRW<[HWWriteResGroup71], (instregex "VCVTPS2PDYrr")>;
def HWWriteResGroup72 : SchedWriteRes<[HWPort0,HWPort0156]> {
let Latency = 4;
@@ -1532,13 +1521,6 @@ def HWWriteResGroup77 : SchedWriteRes<[H
}
def: InstRW<[HWWriteResGroup77], (instregex "VCVTPS2PDYrm")>;
-def HWWriteResGroup77_1 : SchedWriteRes<[HWPort0,HWPort5,HWPort23]> {
- let Latency = 11;
- let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
-}
-def: InstRW<[HWWriteResGroup77_1], (instregex "VPTESTYrm")>;
-
def HWWriteResGroup78 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> {
let Latency = 10;
let NumMicroOps = 3;
Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=331757&r1=331756&r2=331757&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Tue May 8 03:28:03 2018
@@ -200,6 +200,8 @@ defm : SBWriteResPair<WriteFRnd, [SB
defm : SBWriteResPair<WriteFRndY, [SBPort1], 3, [1], 1, 7>;
defm : SBWriteResPair<WriteFLogic, [SBPort5], 1, [1], 1, 6>;
defm : SBWriteResPair<WriteFLogicY, [SBPort5], 1, [1], 1, 7>;
+defm : SBWriteResPair<WriteFTest, [SBPort0], 1, [1], 1, 6>;
+defm : SBWriteResPair<WriteFTestY, [SBPort0], 1, [1], 1, 7>;
defm : SBWriteResPair<WriteFShuffle, [SBPort5], 1, [1], 1, 6>;
defm : SBWriteResPair<WriteFShuffleY,[SBPort5], 1, [1], 1, 7>;
defm : SBWriteResPair<WriteFVarShuffle, [SBPort5], 1, [1], 1, 6>;
@@ -217,6 +219,8 @@ def : WriteRes<WriteVecMove, [SB
defm : SBWriteResPair<WriteVecLogic, [SBPort015], 1, [1], 1, 6>;
defm : SBWriteResPair<WriteVecLogicY,[SBPort015], 1, [1], 1, 7>;
+defm : SBWriteResPair<WriteVecTest, [SBPort0,SBPort5], 2, [1,1], 2, 6>;
+defm : SBWriteResPair<WriteVecTestY, [SBPort0,SBPort5], 2, [1,1], 2, 7>;
defm : SBWriteResPair<WriteVecALU, [SBPort15], 1, [1], 1, 6>;
defm : SBWriteResPair<WriteVecALUY, [SBPort15], 1, [1], 1, 7>;
defm : SBWriteResPair<WriteVecIMul, [SBPort0], 5, [1], 1, 5>;
@@ -399,9 +403,7 @@ def SBWriteResGroup0 : SchedWriteRes<[SB
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SBWriteResGroup0], (instregex "(V?)CVTSS2SDrr",
- "VTESTPD(Y?)rr",
- "VTESTPS(Y?)rr")>;
+def: InstRW<[SBWriteResGroup0], (instregex "(V?)CVTSS2SDrr")>;
def SBWriteResGroup1 : SchedWriteRes<[SBPort1]> {
let Latency = 1;
@@ -536,8 +538,7 @@ def SBWriteResGroup13 : SchedWriteRes<[S
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SBWriteResGroup13], (instregex "(V?)CVTPS2PD(Y?)rr",
- "(V?)PTEST(Y?)rr")>;
+def: InstRW<[SBWriteResGroup13], (instregex "(V?)CVTPS2PD(Y?)rr")>;
def SBWriteResGroup15 : SchedWriteRes<[SBPort0,SBPort015]> {
let Latency = 2;
@@ -929,9 +930,7 @@ def SBWriteResGroup55 : SchedWriteRes<[S
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup55], (instregex "(V?)CVTPS2PD(Y?)rm",
- "(V?)CVTSS2SDrm",
- "VTESTPDrm",
- "VTESTPSrm")>;
+ "(V?)CVTSS2SDrm")>;
def SBWriteResGroup58 : SchedWriteRes<[SBPort23,SBPort05]> {
let Latency = 7;
@@ -1054,14 +1053,6 @@ def: InstRW<[SBWriteResGroup69], (instre
"SHR(8|16|32|64)m1",
"SHR(8|16|32|64)mi")>;
-def SBWriteResGroup71 : SchedWriteRes<[SBPort0,SBPort23]> {
- let Latency = 8;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[SBWriteResGroup71], (instregex "VTESTPDYrm",
- "VTESTPSYrm")>;
-
def SBWriteResGroup72 : SchedWriteRes<[SBPort1,SBPort23]> {
let Latency = 8;
let NumMicroOps = 2;
@@ -1087,13 +1078,6 @@ def: InstRW<[SBWriteResGroup77], (instre
"(V?)UCOMISDrm",
"(V?)UCOMISSrm")>;
-def SBWriteResGroup78 : SchedWriteRes<[SBPort0,SBPort5,SBPort23]> {
- let Latency = 8;
- let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
-}
-def: InstRW<[SBWriteResGroup78], (instregex "(V?)PTESTrm")>;
-
def SBWriteResGroup80 : SchedWriteRes<[SBPort23,SBPort15]> {
let Latency = 8;
let NumMicroOps = 4;
@@ -1235,13 +1219,6 @@ def SBWriteResGroup93_4 : SchedWriteRes<
}
def: InstRW<[SBWriteResGroup93_4], (instrs IMUL16rmi, IMUL16rmi8)>;
-def SBWriteResGroup94 : SchedWriteRes<[SBPort0,SBPort5,SBPort23]> {
- let Latency = 9;
- let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
-}
-def: InstRW<[SBWriteResGroup94], (instregex "VPTESTYrm")>;
-
def SBWriteResGroup95 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> {
let Latency = 9;
let NumMicroOps = 3;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=331757&r1=331756&r2=331757&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Tue May 8 03:28:03 2018
@@ -213,6 +213,8 @@ defm : SKLWriteResPair<WriteFRnd, [S
defm : SKLWriteResPair<WriteFRndY, [SKLPort01], 8, [2], 2, 7>; // Floating point rounding (YMM/ZMM).
defm : SKLWriteResPair<WriteFLogic, [SKLPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals.
defm : SKLWriteResPair<WriteFLogicY, [SKLPort015], 1, [1], 1, 7>; // Floating point and/or/xor logicals (YMM/ZMM).
+defm : SKLWriteResPair<WriteFTest, [SKLPort0], 2, [1], 1, 6>; // Floating point TEST instructions.
+defm : SKLWriteResPair<WriteFTestY, [SKLPort0], 2, [1], 1, 7>; // Floating point TEST instructions (YMM/ZMM).
defm : SKLWriteResPair<WriteFShuffle, [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles.
defm : SKLWriteResPair<WriteFShuffleY, [SKLPort5], 1, [1], 1, 7>; // Floating point vector shuffles (YMM/ZMM).
defm : SKLWriteResPair<WriteFVarShuffle, [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles.
@@ -240,6 +242,8 @@ defm : SKLWriteResPair<WriteVecALU, [S
defm : SKLWriteResPair<WriteVecALUY, [SKLPort01], 1, [1], 1, 7>; // Vector integer ALU op, no logicals (YMM/ZMM).
defm : SKLWriteResPair<WriteVecLogic, [SKLPort015], 1, [1], 1, 6>; // Vector integer and/or/xor.
defm : SKLWriteResPair<WriteVecLogicY,[SKLPort015], 1, [1], 1, 7>; // Vector integer and/or/xor (YMM/ZMM).
+defm : SKLWriteResPair<WriteVecTest, [SKLPort0,SKLPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions.
+defm : SKLWriteResPair<WriteVecTestY, [SKLPort0,SKLPort5], 3, [1,1], 2, 7>; // Vector integer TEST instructions (YMM/ZMM).
defm : SKLWriteResPair<WriteVecIMul, [SKLPort0] , 4, [1], 1, 5>; // Vector integer multiply.
defm : SKLWriteResPair<WriteVecIMulX, [SKLPort01], 4, [1], 1, 6>; // Vector integer multiply (XMM).
defm : SKLWriteResPair<WriteVecIMulY, [SKLPort01], 4, [1], 1, 7>; // Vector integer multiply (YMM/ZMM).
@@ -604,9 +608,7 @@ def SKLWriteResGroup12 : SchedWriteRes<[
def: InstRW<[SKLWriteResGroup12], (instregex "MMX_MOVD64from64rr",
"MMX_MOVD64grr",
"(V?)MOVPDI2DIrr",
- "(V?)MOVPQIto64rr",
- "VTESTPD(Y?)rr",
- "VTESTPS(Y?)rr")>;
+ "(V?)MOVPQIto64rr")>;
def SKLWriteResGroup13 : SchedWriteRes<[SKLPort5]> {
let Latency = 2;
@@ -748,13 +750,6 @@ def: InstRW<[SKLWriteResGroup30], (instr
"VPBROADCASTWrr",
"(V?)PCMPGTQ(Y?)rr")>;
-def SKLWriteResGroup31 : SchedWriteRes<[SKLPort0,SKLPort5]> {
- let Latency = 3;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[SKLWriteResGroup31], (instregex "(V?)PTEST(Y?)rr")>;
-
def SKLWriteResGroup32 : SchedWriteRes<[SKLPort0,SKLPort0156]> {
let Latency = 3;
let NumMicroOps = 2;
@@ -1344,14 +1339,6 @@ def SKLWriteResGroup103 : SchedWriteRes<
}
def: InstRW<[SKLWriteResGroup103], (instrs LOOP)>;
-def SKLWriteResGroup106 : SchedWriteRes<[SKLPort0,SKLPort23]> {
- let Latency = 8;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[SKLWriteResGroup106], (instregex "VTESTPDrm",
- "VTESTPSrm")>;
-
def SKLWriteResGroup107 : SchedWriteRes<[SKLPort1,SKLPort23]> {
let Latency = 8;
let NumMicroOps = 2;
@@ -1473,9 +1460,7 @@ def SKLWriteResGroup120 : SchedWriteRes<
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup120], (instregex "MMX_CVTPI2PSirm",
- "VTESTPDYrm",
- "VTESTPSYrm")>;
+def: InstRW<[SKLWriteResGroup120], (instregex "MMX_CVTPI2PSirm")>;
def SKLWriteResGroup121 : SchedWriteRes<[SKLPort5,SKLPort23]> {
let Latency = 9;
@@ -1498,13 +1483,6 @@ def: InstRW<[SKLWriteResGroup123], (inst
"VCVTPH2PSrm",
"(V?)CVTPS2PDrm")>;
-def SKLWriteResGroup126 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
- let Latency = 9;
- let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
-}
-def: InstRW<[SKLWriteResGroup126], (instregex "(V?)PTESTrm")>;
-
def SKLWriteResGroup127 : SchedWriteRes<[SKLPort1,SKLPort5,SKLPort23]> {
let Latency = 9;
let NumMicroOps = 3;
@@ -1561,8 +1539,7 @@ def SKLWriteResGroup138 : SchedWriteRes<
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKLWriteResGroup138], (instregex "MMX_CVTPI2PDirm",
- "VPTESTYrm")>;
+def: InstRW<[SKLWriteResGroup138], (instregex "MMX_CVTPI2PDirm")>;
def SKLWriteResGroup139 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> {
let Latency = 10;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=331757&r1=331756&r2=331757&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Tue May 8 03:28:03 2018
@@ -213,6 +213,8 @@ defm : SKXWriteResPair<WriteFRnd, [SKX
defm : SKXWriteResPair<WriteFRndY, [SKXPort015], 8, [2], 2, 7>; // Floating point rounding (YMM/ZMM).
defm : SKXWriteResPair<WriteFLogic, [SKXPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals.
defm : SKXWriteResPair<WriteFLogicY, [SKXPort015], 1, [1], 1, 7>; // Floating point and/or/xor logicals (YMM/ZMM).
+defm : SKXWriteResPair<WriteFTest, [SKXPort0], 2, [1], 1, 6>; // Floating point TEST instructions.
+defm : SKXWriteResPair<WriteFTestY, [SKXPort0], 2, [1], 1, 7>; // Floating point TEST instructions (YMM/ZMM).
defm : SKXWriteResPair<WriteFShuffle, [SKXPort5], 1, [1], 1, 6>; // Floating point vector shuffles.
defm : SKXWriteResPair<WriteFShuffleY, [SKXPort5], 1, [1], 1, 7>; // Floating point vector shuffles (YMM/ZMM).
defm : SKXWriteResPair<WriteFVarShuffle, [SKXPort5], 1, [1], 1, 6>; // Floating point vector variable shuffles.
@@ -240,6 +242,8 @@ defm : SKXWriteResPair<WriteVecALU, [S
defm : SKXWriteResPair<WriteVecALUY, [SKXPort01], 1, [1], 1, 7>; // Vector integer ALU op, no logicals (YMM/ZMM).
defm : SKXWriteResPair<WriteVecLogic, [SKXPort015], 1, [1], 1, 6>; // Vector integer and/or/xor.
defm : SKXWriteResPair<WriteVecLogicY,[SKXPort015], 1, [1], 1, 7>; // Vector integer and/or/xor (YMM/ZMM).
+defm : SKXWriteResPair<WriteVecTest, [SKXPort0,SKXPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions.
+defm : SKXWriteResPair<WriteVecTestY, [SKXPort0,SKXPort5], 3, [1,1], 2, 7>; // Vector integer TEST instructions (YMM/ZMM).
defm : SKXWriteResPair<WriteVecIMul, [SKXPort0], 4, [1], 1, 5>; // Vector integer multiply.
defm : SKXWriteResPair<WriteVecIMulX, [SKXPort015], 4, [1], 1, 6>; // Vector integer multiply (XMM).
defm : SKXWriteResPair<WriteVecIMulY, [SKXPort015], 4, [1], 1, 7>; // Vector integer multiply (YMM/ZMM).
@@ -803,11 +807,7 @@ def: InstRW<[SKXWriteResGroup12], (instr
"VMOVPDI2DIZrr",
"VMOVPDI2DIrr",
"VMOVPQIto64Zrr",
- "VMOVPQIto64rr",
- "VTESTPDYrr",
- "VTESTPDrr",
- "VTESTPSYrr",
- "VTESTPSrr")>;
+ "VMOVPQIto64rr")>;
def SKXWriteResGroup13 : SchedWriteRes<[SKXPort5]> {
let Latency = 2;
@@ -1103,13 +1103,6 @@ def: InstRW<[SKXWriteResGroup32], (instr
"VPTESTNMWZ256rr",
"VPTESTNMWZrr")>;
-def SKXWriteResGroup33 : SchedWriteRes<[SKXPort0,SKXPort5]> {
- let Latency = 3;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[SKXWriteResGroup33], (instregex "(V?)PTEST(Y?)rr")>;
-
def SKXWriteResGroup34 : SchedWriteRes<[SKXPort0,SKXPort0156]> {
let Latency = 3;
let NumMicroOps = 2;
@@ -2149,14 +2142,6 @@ def SKXWriteResGroup114 : SchedWriteRes<
}
def: InstRW<[SKXWriteResGroup114], (instrs VSCATTERDPSZmr)>;
-def SKXWriteResGroup117 : SchedWriteRes<[SKXPort0,SKXPort23]> {
- let Latency = 8;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[SKXWriteResGroup117], (instregex "VTESTPDrm",
- "VTESTPSrm")>;
-
def SKXWriteResGroup118 : SchedWriteRes<[SKXPort1,SKXPort23]> {
let Latency = 8;
let NumMicroOps = 2;
@@ -2410,9 +2395,7 @@ def SKXWriteResGroup135 : SchedWriteRes<
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKXWriteResGroup135], (instregex "MMX_CVTPI2PSirm",
- "VTESTPDYrm",
- "VTESTPSYrm")>;
+def: InstRW<[SKXWriteResGroup135], (instregex "MMX_CVTPI2PSirm")>;
def SKXWriteResGroup136 : SchedWriteRes<[SKXPort5,SKXPort23]> {
let Latency = 9;
@@ -2500,13 +2483,6 @@ def: InstRW<[SKXWriteResGroup138], (inst
"VRSQRT14PDZr(b?)",
"VRSQRT14PSZr(b?)")>;
-def SKXWriteResGroup141 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
- let Latency = 9;
- let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
-}
-def: InstRW<[SKXWriteResGroup141], (instregex "(V?)PTESTrm")>;
-
def SKXWriteResGroup142 : SchedWriteRes<[SKXPort1,SKXPort5,SKXPort23]> {
let Latency = 9;
let NumMicroOps = 3;
@@ -2664,8 +2640,7 @@ def SKXWriteResGroup152 : SchedWriteRes<
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKXWriteResGroup152], (instregex "MMX_CVTPI2PDirm",
- "VPTESTYrm")>;
+def: InstRW<[SKXWriteResGroup152], (instregex "MMX_CVTPI2PDirm")>;
def SKXWriteResGroup153 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
let Latency = 10;
Modified: llvm/trunk/lib/Target/X86/X86Schedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Schedule.td?rev=331757&r1=331756&r2=331757&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Schedule.td (original)
+++ llvm/trunk/lib/Target/X86/X86Schedule.td Tue May 8 03:28:03 2018
@@ -162,6 +162,8 @@ defm WriteFRnd : X86SchedWritePair; //
defm WriteFRndY : X86SchedWritePair; // Floating point rounding (YMM/ZMM).
defm WriteFLogic : X86SchedWritePair; // Floating point and/or/xor logicals.
defm WriteFLogicY : X86SchedWritePair; // Floating point and/or/xor logicals (YMM/ZMM).
+defm WriteFTest : X86SchedWritePair; // Floating point TEST instructions.
+defm WriteFTestY : X86SchedWritePair; // Floating point TEST instructions (YMM/ZMM).
defm WriteFShuffle : X86SchedWritePair; // Floating point vector shuffles.
defm WriteFShuffleY : X86SchedWritePair; // Floating point vector shuffles (YMM/ZMM).
defm WriteFVarShuffle : X86SchedWritePair; // Floating point vector variable shuffles.
@@ -184,10 +186,13 @@ defm WritePHAddY : X86SchedWritePair; //
def WriteVecLoad : SchedWrite;
def WriteVecStore : SchedWrite;
def WriteVecMove : SchedWrite;
+
defm WriteVecALU : X86SchedWritePair; // Vector integer ALU op, no logicals.
defm WriteVecALUY : X86SchedWritePair; // Vector integer ALU op, no logicals (YMM/ZMM).
defm WriteVecLogic : X86SchedWritePair; // Vector integer and/or/xor logicals.
defm WriteVecLogicY: X86SchedWritePair; // Vector integer and/or/xor logicals (YMM/ZMM).
+defm WriteVecTest : X86SchedWritePair; // Vector integer TEST instructions.
+defm WriteVecTestY : X86SchedWritePair; // Vector integer TEST instructions (YMM/ZMM).
defm WriteVecShift : X86SchedWritePair; // Vector integer shifts (default).
defm WriteVecShiftX : X86SchedWritePair; // Vector integer shifts (XMM).
defm WriteVecShiftY : X86SchedWritePair; // Vector integer shifts (YMM/ZMM).
@@ -317,6 +322,8 @@ def SchedWriteFRnd
: X86SchedWriteWidths<WriteFRnd, WriteFRnd, WriteFRndY, WriteFRndY>;
def SchedWriteFLogic
: X86SchedWriteWidths<WriteFLogic, WriteFLogic, WriteFLogicY, WriteFLogicY>;
+def SchedWriteFTest
+ : X86SchedWriteWidths<WriteFTest, WriteFTest, WriteFTestY, WriteFTestY>;
def SchedWriteFShuffle
: X86SchedWriteWidths<WriteFShuffle, WriteFShuffle,
@@ -337,6 +344,9 @@ def SchedWritePHAdd
def SchedWriteVecLogic
: X86SchedWriteWidths<WriteVecLogic, WriteVecLogic,
WriteVecLogicY, WriteVecLogicY>;
+def SchedWriteVecTest
+ : X86SchedWriteWidths<WriteVecTest, WriteVecTest,
+ WriteVecTestY, WriteVecTestY>;
def SchedWriteVecShift
: X86SchedWriteWidths<WriteVecShift, WriteVecShiftX,
WriteVecShiftY, WriteVecShiftY>;
Modified: llvm/trunk/lib/Target/X86/X86ScheduleAtom.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleAtom.td?rev=331757&r1=331756&r2=331757&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleAtom.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleAtom.td Tue May 8 03:28:03 2018
@@ -250,6 +250,8 @@ defm : AtomWriteResPair<WriteFRnd,
defm : AtomWriteResPair<WriteFRndY, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
defm : AtomWriteResPair<WriteFLogic, [AtomPort01], [AtomPort0]>;
defm : AtomWriteResPair<WriteFLogicY, [AtomPort01], [AtomPort0]>; // NOTE: Doesn't exist on Atom.
+defm : AtomWriteResPair<WriteFTest, [AtomPort01], [AtomPort0]>;
+defm : AtomWriteResPair<WriteFTestY , [AtomPort01], [AtomPort0]>; // NOTE: Doesn't exist on Atom.
defm : AtomWriteResPair<WriteFShuffle, [AtomPort0], [AtomPort0]>;
defm : AtomWriteResPair<WriteFShuffleY, [AtomPort0], [AtomPort0]>; // NOTE: Doesn't exist on Atom.
defm : AtomWriteResPair<WriteFVarShuffle, [AtomPort0], [AtomPort0]>; // NOTE: Doesn't exist on Atom.
@@ -288,6 +290,8 @@ defm : AtomWriteResPair<WriteVecALU,
defm : AtomWriteResPair<WriteVecALUY, [AtomPort01], [AtomPort0], 1, 1>;
defm : AtomWriteResPair<WriteVecLogic, [AtomPort01], [AtomPort0], 1, 1>;
defm : AtomWriteResPair<WriteVecLogicY, [AtomPort01], [AtomPort0], 1, 1>;
+defm : AtomWriteResPair<WriteVecTest, [AtomPort01], [AtomPort0], 1, 1>;
+defm : AtomWriteResPair<WriteVecTestY, [AtomPort01], [AtomPort0], 1, 1>;
defm : AtomWriteResPair<WriteVecShift, [AtomPort01], [AtomPort01], 2, 3, [2], [3]>;
defm : AtomWriteResPair<WriteVecShiftX, [AtomPort01], [AtomPort01], 2, 3, [2], [3]>;
defm : AtomWriteResPair<WriteVecShiftY, [AtomPort01], [AtomPort01], 2, 3, [2], [3]>;
Modified: llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td?rev=331757&r1=331756&r2=331757&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td Tue May 8 03:28:03 2018
@@ -369,6 +369,8 @@ defm : JWriteResFpuPair<WriteFRnd,
defm : JWriteResYMMPair<WriteFRndY, [JFPU1, JSTC], 3, [2,2], 2>;
defm : JWriteResFpuPair<WriteFLogic, [JFPU01, JFPX], 1>;
defm : JWriteResYMMPair<WriteFLogicY, [JFPU01, JFPX], 1, [2, 2], 2>;
+defm : JWriteResFpuPair<WriteFTest, [JFPU0, JFPA, JALU0], 3>;
+defm : JWriteResYMMPair<WriteFTestY , [JFPU01, JFPX, JFPA, JALU0], 4, [2, 2, 2, 1], 3>;
defm : JWriteResFpuPair<WriteFShuffle, [JFPU01, JFPX], 1>;
defm : JWriteResYMMPair<WriteFShuffleY, [JFPU01, JFPX], 1, [2, 2], 2>;
defm : JWriteResFpuPair<WriteFVarShuffle, [JFPU01, JFPX], 2, [1, 4], 3>;
@@ -464,6 +466,8 @@ defm : JWriteResFpuPair<WriteVarBlend,
defm : JWriteResFpuPair<WriteVarBlendY, [JFPU01, JVALU], 2, [1, 4], 3>;
defm : JWriteResFpuPair<WriteVecLogic, [JFPU01, JVALU], 1>;
defm : JWriteResFpuPair<WriteVecLogicY, [JFPU01, JVALU], 1>; // NOTE: Doesn't exist on Jaguar.
+defm : JWriteResFpuPair<WriteVecTest, [JFPU0, JFPA, JALU0], 3>;
+defm : JWriteResYMMPair<WriteVecTestY , [JFPU01, JFPX, JFPA, JALU0], 4, [2, 2, 2, 1], 3>;
defm : JWriteResFpuPair<WriteShuffle256, [JFPU01, JVALU], 1>;
defm : JWriteResFpuPair<WriteVarShuffle256, [JFPU01, JVALU], 1>; // NOTE: Doesn't exist on Jaguar.
defm : JWriteResFpuPair<WriteVarVecShift, [JFPU01, JVALU], 1>; // NOTE: Doesn't exist on Jaguar.
@@ -644,30 +648,6 @@ def JWriteVMaskMovYSt: SchedWriteRes<[JF
}
def : InstRW<[JWriteVMaskMovYSt], (instrs VMASKMOVPDYmr, VMASKMOVPSYmr)>;
-def JWriteVTESTY: SchedWriteRes<[JFPU01, JFPX, JFPA, JALU0]> {
- let Latency = 4;
- let ResourceCycles = [2, 2, 2, 1];
- let NumMicroOps = 3;
-}
-def : InstRW<[JWriteVTESTY], (instrs VPTESTYrr, VTESTPDYrr, VTESTPSYrr)>;
-
-def JWriteVTESTYLd: SchedWriteRes<[JLAGU, JFPU01, JFPX, JFPA, JALU0]> {
- let Latency = 9;
- let ResourceCycles = [2, 2, 2, 2, 1];
- let NumMicroOps = 3;
-}
-def : InstRW<[JWriteVTESTYLd], (instrs VPTESTYrm, VTESTPDYrm, VTESTPSYrm)>;
-
-def JWriteVTEST: SchedWriteRes<[JFPU0, JFPA, JALU0]> {
- let Latency = 3;
-}
-def : InstRW<[JWriteVTEST], (instrs PTESTrr, VPTESTrr, VTESTPDrr, VTESTPSrr)>;
-
-def JWriteVTESTLd: SchedWriteRes<[JLAGU, JFPU0, JFPA, JALU0]> {
- let Latency = 8;
-}
-def : InstRW<[JWriteVTESTLd], (instrs PTESTrm, VPTESTrm, VTESTPDrm, VTESTPSrm)>;
-
def JWriteJVZEROALL: SchedWriteRes<[]> {
let Latency = 90;
let NumMicroOps = 73;
Modified: llvm/trunk/lib/Target/X86/X86ScheduleSLM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleSLM.td?rev=331757&r1=331756&r2=331757&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleSLM.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleSLM.td Tue May 8 03:28:03 2018
@@ -183,6 +183,8 @@ defm : SLMWriteResPair<WriteFRnd, [SLM
defm : SLMWriteResPair<WriteFRndY, [SLM_FPC_RSV1], 3>;
defm : SLMWriteResPair<WriteFLogic, [SLM_FPC_RSV01], 1>;
defm : SLMWriteResPair<WriteFLogicY, [SLM_FPC_RSV01], 1>;
+defm : SLMWriteResPair<WriteFTest, [SLM_FPC_RSV01], 1>;
+defm : SLMWriteResPair<WriteFTestY, [SLM_FPC_RSV01], 1>;
defm : SLMWriteResPair<WriteFShuffle, [SLM_FPC_RSV0], 1>;
defm : SLMWriteResPair<WriteFShuffleY, [SLM_FPC_RSV0], 1>;
defm : SLMWriteResPair<WriteFVarShuffle, [SLM_FPC_RSV0], 1>;
@@ -203,6 +205,8 @@ defm : SLMWriteResPair<WriteVecShiftImmX
defm : SLMWriteResPair<WriteVecShiftImmY,[SLM_FPC_RSV0], 1>;
defm : SLMWriteResPair<WriteVecLogic, [SLM_FPC_RSV01], 1>;
defm : SLMWriteResPair<WriteVecLogicY,[SLM_FPC_RSV01], 1>;
+defm : SLMWriteResPair<WriteVecTest, [SLM_FPC_RSV01], 1>;
+defm : SLMWriteResPair<WriteVecTestY, [SLM_FPC_RSV01], 1>;
defm : SLMWriteResPair<WriteVecALU, [SLM_FPC_RSV01], 1>;
defm : SLMWriteResPair<WriteVecALUY, [SLM_FPC_RSV01], 1>;
defm : SLMWriteResPair<WriteVecIMul, [SLM_FPC_RSV0], 4>;
Modified: llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td?rev=331757&r1=331756&r2=331757&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td Tue May 8 03:28:03 2018
@@ -227,6 +227,8 @@ defm : ZnWriteResFpuPair<WriteFRnd,
defm : ZnWriteResFpuPair<WriteFRndY, [ZnFPU3], 4, [1], 1, 7, 1>; // FIXME: Should folds require 1 extra uops?
defm : ZnWriteResFpuPair<WriteFLogic, [ZnFPU], 1>;
defm : ZnWriteResFpuPair<WriteFLogicY, [ZnFPU], 1>;
+defm : ZnWriteResFpuPair<WriteFTest, [ZnFPU], 1>;
+defm : ZnWriteResFpuPair<WriteFTestY, [ZnFPU], 1>;
defm : ZnWriteResFpuPair<WriteFShuffle, [ZnFPU12], 1>;
defm : ZnWriteResFpuPair<WriteFShuffleY, [ZnFPU12], 1>;
defm : ZnWriteResFpuPair<WriteFVarShuffle, [ZnFPU12], 1>;
@@ -271,6 +273,8 @@ defm : ZnWriteResFpuPair<WriteVecShiftIm
defm : ZnWriteResFpuPair<WriteVecShiftImmY, [ZnFPU], 1>;
defm : ZnWriteResFpuPair<WriteVecLogic, [ZnFPU], 1>;
defm : ZnWriteResFpuPair<WriteVecLogicY, [ZnFPU], 1>;
+defm : ZnWriteResFpuPair<WriteVecTest, [ZnFPU12], 1, [2], 1, 7, 1>;
+defm : ZnWriteResFpuPair<WriteVecTestY, [ZnFPU12], 1, [2], 1, 7, 1>;
defm : ZnWriteResFpuPair<WriteVecALU, [ZnFPU], 1>;
defm : ZnWriteResFpuPair<WriteVecALUY, [ZnFPU], 1>;
defm : ZnWriteResFpuPair<WriteVecIMul, [ZnFPU0], 4>;
@@ -1101,21 +1105,6 @@ def : InstRW<[ZnWritePMULLDYm], (instreg
//-- Logic instructions --//
-// PTEST.
-// v,v.
-def ZnWritePTESTr : SchedWriteRes<[ZnFPU12]> {
- let ResourceCycles = [2];
-}
-def : InstRW<[ZnWritePTESTr], (instregex "(V?)PTEST(Y?)rr")>;
-
-// v,m.
-def ZnWritePTESTm : SchedWriteRes<[ZnAGU, ZnFPU12]> {
- let Latency = 8;
- let NumMicroOps = 2;
- let ResourceCycles = [1, 2];
-}
-def : InstRW<[ZnWritePTESTm], (instregex "(V?)PTEST(Y?)rm")>;
-
// PSLL,PSRL,PSRA W/D/Q.
// x,x / v,v,x.
def ZnWritePShift : SchedWriteRes<[ZnFPU2]> ;
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