[PATCH] D46470: [AMDGPU] Fixed a couple of SIFixWWMLiveness problems

[Tim Renouf via Phabricator via llvm-commits]

tpr added a comment.

Hi Connor

Thanks for the pointers on possible future directions. I was vaguely thinking about some scheme where a value in a live interval is marked with its predication in some way so two overlapping segments are not considered interfering if they have disjoint predications. But that is pretty intrusive.

Anyway, back to my present problem:

I have been trying to come up with a better way of handling WWM liveness based on examining the particular cases (which are essentially a multi-def value that is a lowered phi, and a single-def value defined at the bottom of a do-while loop that the WWM is inside).

However, a fundamental problem has occurred to me: however we synthesize liveness in WWM code, surely the register allocator could decide to split the register, and the inserted copies will be predicated and thus useless for our live-in-inactive-lanes liveness. The inactive lanes will rely on keeping the value in the original register, but the liveness info will no longer say that register is live in the WWM code, and the same register could be allocated to a WWM value.

Any ideas on that one?


Repository:
  rL LLVM

https://reviews.llvm.org/D46470