[llvm] r331354 - [MIPS] Fix DIV/DIVU scheduling classes.

[Clement Courbet via llvm-commits]

Author: courbet
Date: Wed May  2 06:37:28 2018
New Revision: 331354

URL: http://llvm.org/viewvc/llvm-project?rev=331354&view=rev
Log:
[MIPS] Fix DIV/DIVU scheduling classes.

https://reviews.llvm.org/D46356.

Modified:
    llvm/trunk/lib/Target/Mips/MipsScheduleGeneric.td

Modified: llvm/trunk/lib/Target/Mips/MipsScheduleGeneric.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsScheduleGeneric.td?rev=331354&r1=331353&r2=331354&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsScheduleGeneric.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsScheduleGeneric.td Wed May  2 06:37:28 2018
@@ -74,12 +74,12 @@ def : ItinRW<[GenericWriteMDUtoGPR], [II
 def GenericWriteDIV : SchedWriteRes<[GenericIssueDIV]> {
   // Estimated worst case
   let Latency = 33;
-  let ResourceCycles = [1, 33];
+  let ResourceCycles = [33];
 }
 def GenericWriteDIVU : SchedWriteRes<[GenericIssueDIV]> {
   // Estimated worst case
   let Latency = 31;
-  let ResourceCycles = [1, 31];
+  let ResourceCycles = [31];
 }
 
 def : ItinRW<[GenericWriteDIV], [II_DIV]>;