[PATCH] D46179: [X86] Lowering adds/addus/subs/subus intrinsics to native IR (LLVM part)

[Tomasz Krupa via Phabricator via llvm-commits]

tkrupa marked 3 inline comments as done.
tkrupa added inline comments.


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Comment at: lib/Target/X86/X86ISelLowering.cpp:36183
+  // as those before extension.
+  if (LHS.getValueType() != VT || RHS.getValueType() != VT)
+    return SDValue();
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craig.topper wrote:
> Oh I see, you covered for that case here. But do we really need to do this? Can we just make smaller extends?
No - detectSSatPattern and detectUSatPattern check for min/max values of destination type (VT here), so we cannot change that.
However, if element type before extension is smaller than in VT, the overflow/underflow never occurs. Can we just emit ISD::ADD/ISD::SUB in such cases?


Repository:
  rL LLVM

https://reviews.llvm.org/D46179