[PATCH] D46133: [InstCombine, ARM, AArch64] Convert table lookup to shuffle vector

[Alexandros Lamprineas via Phabricator via llvm-commits]

labrinea added a comment.

Good catch. The current patch hits the assertion when handling the llvm.aarch64.neon.tbl1.v16i8 inrinsic, because NumElts is 16. Does it make sense to perform the transformation in this case? I could get rid of the assert and bail the optimization if NumElts neither 8 nor 16 (or just 8).


https://reviews.llvm.org/D46133