[llvm] r331341 - [mips] Correct the predicates for shifts.
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Wed May 2 02:55:49 PDT 2018
Author: sdardis
Date: Wed May 2 02:55:49 2018
New Revision: 331341
URL: http://llvm.org/viewvc/llvm-project?rev=331341&view=rev
Log:
[mips] Correct the predicates for shifts.
Reviewers: smaksimovic, abeserminji, atanasyan
Differential Revision: https://reviews.llvm.org/D46123
Modified:
llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/MC/Mips/micromips/valid.s
llvm/trunk/test/MC/Mips/mips1/valid.s
llvm/trunk/test/MC/Mips/mips2/valid.s
llvm/trunk/test/MC/Mips/mips3/valid.s
llvm/trunk/test/MC/Mips/mips32/valid.s
llvm/trunk/test/MC/Mips/mips32r2/valid.s
llvm/trunk/test/MC/Mips/mips32r3/valid.s
llvm/trunk/test/MC/Mips/mips32r5/valid.s
llvm/trunk/test/MC/Mips/mips32r6/valid.s
llvm/trunk/test/MC/Mips/mips4/valid.s
llvm/trunk/test/MC/Mips/mips5/valid.s
llvm/trunk/test/MC/Mips/mips64/valid.s
llvm/trunk/test/MC/Mips/mips64r2/valid.s
llvm/trunk/test/MC/Mips/mips64r3/valid.s
llvm/trunk/test/MC/Mips/mips64r5/valid.s
llvm/trunk/test/MC/Mips/mips64r6/valid.s
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=331341&r1=331340&r2=331341&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Wed May 2 02:55:49 2018
@@ -769,17 +769,17 @@ let DecoderNamespace = "MicroMips", Pred
/// Shift Instructions
def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
- SRA_FM_MM<0, 0>;
+ SRA_FM_MM<0, 0>, ISA_MICROMIPS;
def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
- SRA_FM_MM<0x40, 0>;
+ SRA_FM_MM<0x40, 0>, ISA_MICROMIPS;
def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
- SRA_FM_MM<0x80, 0>;
+ SRA_FM_MM<0x80, 0>, ISA_MICROMIPS;
def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
- SRLV_FM_MM<0x10, 0>;
+ SRLV_FM_MM<0x10, 0>, ISA_MICROMIPS;
def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
- SRLV_FM_MM<0x50, 0>;
+ SRLV_FM_MM<0x50, 0>, ISA_MICROMIPS;
def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
- SRLV_FM_MM<0x90, 0>;
+ SRLV_FM_MM<0x90, 0>, ISA_MICROMIPS;
def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
SRA_FM_MM<0xc0, 0> {
list<dag> Pattern = [(set GPR32Opnd:$rd,
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=331341&r1=331340&r2=331341&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Wed May 2 02:55:49 2018
@@ -2010,24 +2010,22 @@ let AdditionalPredicates = [NotInMicroMi
def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
}
-/// Shift Instructions
let AdditionalPredicates = [NotInMicroMips] in {
-def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
- immZExt5>, SRA_FM<0, 0>;
-def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
- immZExt5>, SRA_FM<2, 0>;
-def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
- immZExt5>, SRA_FM<3, 0>;
-def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
- SRLV_FM<4, 0>;
-def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
- SRLV_FM<6, 0>;
-def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
- SRLV_FM<7, 0>;
-}
+ /// Shift Instructions
+ def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
+ immZExt5>, SRA_FM<0, 0>, ISA_MIPS1;
+ def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
+ immZExt5>, SRA_FM<2, 0>, ISA_MIPS1;
+ def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
+ immZExt5>, SRA_FM<3, 0>, ISA_MIPS1;
+ def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
+ SRLV_FM<4, 0>, ISA_MIPS1;
+ def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
+ SRLV_FM<6, 0>, ISA_MIPS1;
+ def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
+ SRLV_FM<7, 0>, ISA_MIPS1;
-// Rotate Instructions
-let AdditionalPredicates = [NotInMicroMips] in {
+ // Rotate Instructions
def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
immZExt5>,
SRA_FM<2, 1>, ISA_MIPS32R2;
Modified: llvm/trunk/test/MC/Mips/micromips/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips/valid.s?rev=331341&r1=331340&r2=331341&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips/valid.s Wed May 2 02:55:49 2018
@@ -97,11 +97,17 @@ div.d $f0, $f2, $f4 # CHECK: div
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FDIV_D32_MM
divu $zero, $9, $7 # CHECK: divu $zero, $9, $7 # encoding: [0x00,0xe9,0xbb,0x3c]
sll $4, $3, 7 # CHECK: sll $4, $3, 7 # encoding: [0x00,0x83,0x38,0x00]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL_MM
sllv $2, $3, $5 # CHECK: sllv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x10]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV_MM
sra $4, $3, 7 # CHECK: sra $4, $3, 7 # encoding: [0x00,0x83,0x38,0x80]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA_MM
srav $2, $3, $5 # CHECK: srav $2, $3, $5 # encoding: [0x00,0x65,0x10,0x90]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRAV_MM
srl $4, $3, 7 # CHECK: srl $4, $3, 7 # encoding: [0x00,0x83,0x38,0x40]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL_MM
srlv $2, $3, $5 # CHECK: srlv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x50]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRLV_MM
rotr $9, $6, 7 # CHECK: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0]
rotrv $9, $6, $7 # CHECK: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0]
lb $5, 8($4) # CHECK: lb $5, 8($4) # encoding: [0x1c,0xa4,0x00,0x08]
Modified: llvm/trunk/test/MC/Mips/mips1/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips1/valid.s?rev=331341&r1=331340&r2=331341&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips1/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips1/valid.s Wed May 2 02:55:49 2018
@@ -109,25 +109,55 @@ a:
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sh $14,-6704($15)
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLLV_MM
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11]
sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b]
sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRAV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRAV_MM
srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRLV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRLV_MM
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SSNOP
# CHECK-NOT: # <MCInst #{{[0-9]+}} SSNOP_MM
Modified: llvm/trunk/test/MC/Mips/mips2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips2/valid.s?rev=331341&r1=331340&r2=331341&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips2/valid.s Wed May 2 02:55:49 2018
@@ -135,11 +135,22 @@ a:
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
- sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
sh $14,-6704($15)
+ sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
+ sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLLV_MM
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11]
@@ -151,15 +162,35 @@ a:
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRAV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRAV_MM
srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRLV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRLV_MM
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12
sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36]
Modified: llvm/trunk/test/MC/Mips/mips3/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips3/valid.s?rev=331341&r1=331340&r2=331341&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips3/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips3/valid.s Wed May 2 02:55:49 2018
@@ -195,10 +195,20 @@ a:
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sh $14,-6704($15)
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLLV_MM
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11]
sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
@@ -207,15 +217,35 @@ a:
sqrt.d $f17,$f22
sqrt.s $f0,$f1
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRAV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRAV_MM
srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRLV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRLV_MM
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12
sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36]
Modified: llvm/trunk/test/MC/Mips/mips32/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32/valid.s?rev=331341&r1=331340&r2=331341&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32/valid.s Wed May 2 02:55:49 2018
@@ -199,10 +199,20 @@ a:
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sh $14,-6704($15)
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLLV_MM
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11]
sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
@@ -213,15 +223,35 @@ a:
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRAV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRAV_MM
srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRLV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRLV_MM
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12
sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36]
Modified: llvm/trunk/test/MC/Mips/mips32r2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r2/valid.s?rev=331341&r1=331340&r2=331341&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r2/valid.s Wed May 2 02:55:49 2018
@@ -244,10 +244,20 @@ a:
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sh $14,-6704($15)
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLLV_MM
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11]
sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
@@ -258,15 +268,35 @@ a:
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRAV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRAV_MM
srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRLV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRLV_MM
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12
sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36]
Modified: llvm/trunk/test/MC/Mips/mips32r3/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r3/valid.s?rev=331341&r1=331340&r2=331341&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r3/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r3/valid.s Wed May 2 02:55:49 2018
@@ -244,10 +244,20 @@ a:
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sh $14,-6704($15)
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLLV_MM
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11]
sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
@@ -258,15 +268,35 @@ a:
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRAV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRAV_MM
srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRLV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRLV_MM
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12
sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36]
Modified: llvm/trunk/test/MC/Mips/mips32r5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r5/valid.s?rev=331341&r1=331340&r2=331341&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r5/valid.s Wed May 2 02:55:49 2018
@@ -245,10 +245,20 @@ a:
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sh $14,-6704($15)
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLLV_MM
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11]
sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
@@ -259,15 +269,35 @@ a:
sqrt.s $f0, $f12 # CHECK: sqrt.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FSQRT_S
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRAV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRAV_MM
srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRLV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRLV_MM
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12
sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36]
Modified: llvm/trunk/test/MC/Mips/mips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r6/valid.s?rev=331341&r1=331340&r2=331341&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r6/valid.s Wed May 2 02:55:49 2018
@@ -208,9 +208,51 @@ a:
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
- sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
- sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
- srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
+ sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
+ sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
+ sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
+ sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
+ sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLLV_MM
+ sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
+ sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
+ sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
+ sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
+ srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRAV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRAV_MM
+ srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
+ srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
+ srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
+ srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
+ srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRLV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRLV_MM
ssnop # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS32r6 and is equivalent to a nop instruction
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sdbbp # CHECK: sdbbp # encoding: [0x00,0x00,0x00,0x0e]
Modified: llvm/trunk/test/MC/Mips/mips4/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips4/valid.s?rev=331341&r1=331340&r2=331341&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips4/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips4/valid.s Wed May 2 02:55:49 2018
@@ -255,10 +255,20 @@ a:
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sh $14,-6704($15)
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLLV_MM
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11]
sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
@@ -267,15 +277,35 @@ a:
sqrt.d $f17,$f22
sqrt.s $f0,$f1
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRAV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRAV_MM
srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRLV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRLV_MM
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12
sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36]
Modified: llvm/trunk/test/MC/Mips/mips5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips5/valid.s?rev=331341&r1=331340&r2=331341&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips5/valid.s Wed May 2 02:55:49 2018
@@ -256,10 +256,20 @@ a:
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sh $14,-6704($15)
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLLV_MM
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11]
sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
@@ -268,15 +278,35 @@ a:
sqrt.d $f17,$f22
sqrt.s $f0,$f1
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRAV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRAV_MM
srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRLV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRLV_MM
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12
sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36]
Modified: llvm/trunk/test/MC/Mips/mips64/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64/valid.s?rev=331341&r1=331340&r2=331341&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64/valid.s Wed May 2 02:55:49 2018
@@ -274,10 +274,20 @@ a:
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sh $14,-6704($15)
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLLV_MM
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11]
sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
@@ -286,15 +296,35 @@ a:
sqrt.d $f17,$f22
sqrt.s $f0,$f1
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRAV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRAV_MM
srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRLV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRLV_MM
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12
sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36]
Modified: llvm/trunk/test/MC/Mips/mips64r2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r2/valid.s?rev=331341&r1=331340&r2=331341&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r2/valid.s Wed May 2 02:55:49 2018
@@ -314,10 +314,20 @@ a:
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sh $14,-6704($15)
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLLV_MM
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11]
sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
@@ -325,16 +335,36 @@ a:
sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
sqrt.d $f17,$f22
sqrt.s $f0,$f1
- sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
+ sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
- srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRAV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRAV_MM
srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
+ srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRLV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRLV_MM
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12
sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36]
Modified: llvm/trunk/test/MC/Mips/mips64r3/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r3/valid.s?rev=331341&r1=331340&r2=331341&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r3/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r3/valid.s Wed May 2 02:55:49 2018
@@ -303,10 +303,21 @@ a:
seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
sh $14,-6704($15)
+ sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLLV_MM
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11]
sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
@@ -314,14 +325,36 @@ a:
sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
sqrt.d $f17,$f22
sqrt.s $f0,$f1
+ sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRAV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRAV_MM
+ srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRLV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRLV_MM
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12
sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36]
Modified: llvm/trunk/test/MC/Mips/mips64r5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r5/valid.s?rev=331341&r1=331340&r2=331341&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r5/valid.s Wed May 2 02:55:49 2018
@@ -309,10 +309,20 @@ a:
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
sh $14,-6704($15)
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLLV_MM
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11]
sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
@@ -320,16 +330,36 @@ a:
sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
sqrt.d $f17,$f22
sqrt.s $f0,$f1
- sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
+ sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
- srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRAV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRAV_MM
srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
+ srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRLV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRLV_MM
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12
sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36]
Modified: llvm/trunk/test/MC/Mips/mips64r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r6/valid.s?rev=331341&r1=331340&r2=331341&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r6/valid.s Wed May 2 02:55:49 2018
@@ -247,9 +247,51 @@ a:
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
- sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
- sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
- srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
+ sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
+ sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
+ sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
+ sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
+ sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SLLV_MM
+ sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
+ sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
+ sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
+ sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
+ srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRAV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRAV_MM
+ srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
+ srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
+ srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
+ srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
+ srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRLV
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SRLV_MM
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
ssnop # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS64r6 and is equivalent to a nop instruction
swc2 $25,304($s0) # CHECK: swc2 $25, 304($16) # encoding: [0x49,0x79,0x81,0x30]
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