[PATCH] D46311: [AArch64] added FP16 vcvth intrinsic support

[Luke Geeson via Phabricator via llvm-commits]

LukeGeeson added a comment.

give me one moment, syntax error missed



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Comment at: lib/Target/AArch64/AArch64InstrFormats.td:7799
+                              FPR32, FPR16, vecshiftR32, asm, 
+          []>{
     let Inst{19-16} = imm{3-0};
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SjoerdMeijer wrote:
> nit: don't think you break up the lines like this.
Would you remove line 7803 too? looks better for separation


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Comment at: test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll:131-200
+define dso_local half @test_vcvth_n_f16_s16(i16 %a) local_unnamed_addr #0 {
+entry:
+  %sext = sext i16 %a to i32
+  %fcvth_n = tail call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i32(i32 %sext, i32 1)
+  ret half %fcvth_n
+}
+
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SjoerdMeijer wrote:
> lebedev.ri wrote:
> > Is it intentional that there are no `; CHECK` lines?
> You should add CHECK lines for all these test cases (see examples above).
missed this, will add thanks


Repository:
  rL LLVM

https://reviews.llvm.org/D46311