[PATCH] D46311: [AArch64] added FP16 vcvth intrinsic support

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer added inline comments.


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Comment at: test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=aarch64-eabi -mattr=+v8.2a,+fullfp16  | FileCheck %s
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Please remove this line.


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Comment at: test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll:14
 ; CHECK-LABEL: t_vabdh_f16:
-; CHECK:         fabd h0, h0, h1
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fabd h0, h0, h1
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Please don't modify the existing test cases. There is no need to check for the %bb.0 stuff as it doesn't add any value.


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Comment at: test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll:146
+; CHECK-LABEL: test_vcvth_n_f16_s16:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sxth w8, w0
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Please remove this line here and similar lines in the test cases below.


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Comment at: test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll:147
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sxth w8, w0
+; CHECK-NEXT:    fmov s0, w8
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You should create a regexp for w8, and use it in the line below. Currently the test is very fragile, because if another register gets allocated this test starts failing.


Repository:
  rL LLVM

https://reviews.llvm.org/D46311