[llvm] r331253 - [X86] Tag PSLLDQ/PSRLDQ as WriteShuffle scheduler classes instead of shifts.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Tue May 1 04:05:42 PDT 2018
Author: rksimon
Date: Tue May 1 04:05:42 2018
New Revision: 331253
URL: http://llvm.org/viewvc/llvm-project?rev=331253&view=rev
Log:
[X86] Tag PSLLDQ/PSRLDQ as WriteShuffle scheduler classes instead of shifts.
Although they are encoded similar to bit shifts, the byte shifts behave like shuffles from a scheduling point of view.
Modified:
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
llvm/trunk/lib/Target/X86/X86InstrSSE.td
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=331253&r1=331252&r2=331253&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Tue May 1 04:05:42 2018
@@ -10044,6 +10044,7 @@ defm VSHUFPD: avx512_shufp<"vshufpd", av
// AVX-512 - Byte shift Left/Right
//===----------------------------------------------------------------------===//
+// FIXME: The SSE/AVX names are PSLLDQri etc. - should we add the i here as well?
multiclass avx512_shift_packed<bits<8> opc, SDNode OpNode, Format MRMr,
Format MRMm, string OpcodeStr,
X86FoldableSchedWrite sched, X86VectorVTInfo _>{
@@ -10063,24 +10064,23 @@ multiclass avx512_shift_packed<bits<8> o
multiclass avx512_shift_packed_all<bits<8> opc, SDNode OpNode, Format MRMr,
Format MRMm, string OpcodeStr,
- X86FoldableSchedWrite sched, Predicate prd>{
+ X86SchedWriteWidths sched, Predicate prd>{
let Predicates = [prd] in
- defm Z : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
- OpcodeStr, sched, v64i8_info>, EVEX_V512;
+ defm Z : avx512_shift_packed<opc, OpNode, MRMr, MRMm, OpcodeStr,
+ sched.ZMM, v64i8_info>, EVEX_V512;
let Predicates = [prd, HasVLX] in {
- defm Z256 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
- OpcodeStr, sched, v32i8x_info>, EVEX_V256;
- defm Z128 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
- OpcodeStr, sched, v16i8x_info>, EVEX_V128;
+ defm Z256 : avx512_shift_packed<opc, OpNode, MRMr, MRMm, OpcodeStr,
+ sched.YMM, v32i8x_info>, EVEX_V256;
+ defm Z128 : avx512_shift_packed<opc, OpNode, MRMr, MRMm, OpcodeStr,
+ sched.XMM, v16i8x_info>, EVEX_V128;
}
}
defm VPSLLDQ : avx512_shift_packed_all<0x73, X86vshldq, MRM7r, MRM7m, "vpslldq",
- WriteVecShift, HasBWI>, AVX512PDIi8Base,
- EVEX_4V, VEX_WIG;
+ SchedWriteShuffle, HasBWI>,
+ AVX512PDIi8Base, EVEX_4V, VEX_WIG;
defm VPSRLDQ : avx512_shift_packed_all<0x73, X86vshrdq, MRM3r, MRM3m, "vpsrldq",
- WriteVecShift, HasBWI>, AVX512PDIi8Base,
- EVEX_4V, VEX_WIG;
-
+ SchedWriteShuffle, HasBWI>,
+ AVX512PDIi8Base, EVEX_4V, VEX_WIG;
multiclass avx512_psadbw_packed<bits<8> opc, SDNode OpNode,
string OpcodeStr, X86FoldableSchedWrite sched,
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=331253&r1=331252&r2=331253&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue May 1 04:05:42 2018
@@ -3446,16 +3446,17 @@ multiclass PDI_binop_ri<bits<8> opc, For
}
multiclass PDI_binop_ri_all<bits<8> opc, Format ImmForm, string OpcodeStr,
- SDNode OpNode, X86FoldableSchedWrite sched> {
+ SDNode OpNode, X86SchedWriteWidths sched> {
let Predicates = [HasAVX, NoVLX_Or_NoBWI] in
defm V#NAME : PDI_binop_ri<opc, ImmForm, !strconcat("v", OpcodeStr), OpNode,
- VR128, v16i8, sched, 0>, VEX_4V, VEX_WIG;
+ VR128, v16i8, sched.XMM, 0>, VEX_4V, VEX_WIG;
let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in
defm V#NAME#Y : PDI_binop_ri<opc, ImmForm, !strconcat("v", OpcodeStr), OpNode,
- VR256, v32i8, sched, 0>,
+ VR256, v32i8, sched.YMM, 0>,
VEX_4V, VEX_L, VEX_WIG;
let Constraints = "$src1 = $dst" in
- defm NAME : PDI_binop_ri<opc, ImmForm, OpcodeStr, OpNode, VR128, v16i8, sched>;
+ defm NAME : PDI_binop_ri<opc, ImmForm, OpcodeStr, OpNode, VR128, v16i8,
+ sched.XMM>;
}
let ExeDomain = SSEPackedInt in {
@@ -3481,9 +3482,10 @@ let ExeDomain = SSEPackedInt in {
defm PSRAD : PDI_binop_rmi_all<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
v4i32, v8i32, v4i32, WriteVecShift, NoVLX>;
- defm PSLLDQ : PDI_binop_ri_all<0x73, MRM7r, "pslldq", X86vshldq, WriteVecShift>;
- defm PSRLDQ : PDI_binop_ri_all<0x73, MRM3r, "psrldq", X86vshrdq, WriteVecShift>;
- // PSRADQri doesn't exist in SSE[1-3].
+ defm PSLLDQ : PDI_binop_ri_all<0x73, MRM7r, "pslldq", X86vshldq,
+ SchedWriteShuffle>;
+ defm PSRLDQ : PDI_binop_ri_all<0x73, MRM3r, "psrldq", X86vshrdq,
+ SchedWriteShuffle>;
} // ExeDomain = SSEPackedInt
//===---------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=331253&r1=331252&r2=331253&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Tue May 1 04:05:42 2018
@@ -386,9 +386,7 @@ def: InstRW<[BWWriteResGroup3], (instreg
"MMX_MOVD64to64rr",
"MMX_MOVQ2DQrr",
"(V?)MOV64toPQIrr",
- "(V?)MOVDI2PDIrr",
- "(V?)PSLLDQ(Y?)ri",
- "(V?)PSRLDQ(Y?)ri")>;
+ "(V?)MOVDI2PDIrr")>;
def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> {
let Latency = 1;
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=331253&r1=331252&r2=331253&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Tue May 1 04:05:42 2018
@@ -723,9 +723,7 @@ def: InstRW<[HWWriteResGroup4], (instreg
"MMX_MOVD64to64rr",
"MMX_MOVQ2DQrr",
"(V?)MOV64toPQIrr",
- "(V?)MOVDI2PDIrr",
- "(V?)PSLLDQ(Y?)ri",
- "(V?)PSRLDQ(Y?)ri")>;
+ "(V?)MOVDI2PDIrr")>;
def HWWriteResGroup5 : SchedWriteRes<[HWPort6]> {
let Latency = 1;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=331253&r1=331252&r2=331253&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Tue May 1 04:05:42 2018
@@ -397,9 +397,7 @@ def: InstRW<[SKLWriteResGroup3], (instre
"UCOM_FPr",
"UCOM_Fr",
"(V?)MOV64toPQIrr",
- "(V?)MOVDI2PDIrr",
- "(V?)PSLLDQ(Y?)ri",
- "(V?)PSRLDQ(Y?)ri")>;
+ "(V?)MOVDI2PDIrr")>;
def SKLWriteResGroup4 : SchedWriteRes<[SKLPort6]> {
let Latency = 1;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=331253&r1=331252&r2=331253&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Tue May 1 04:05:42 2018
@@ -445,17 +445,7 @@ def: InstRW<[SKXWriteResGroup3], (instre
"VMOV64toPQIZrr",
"VMOV64toPQIrr",
"VMOVDI2PDIZrr",
- "VMOVDI2PDIrr",
- "VPSLLDQYri",
- "VPSLLDQZ128rr",
- "VPSLLDQZ256rr",
- "VPSLLDQZrr",
- "(V?)PSLLDQri",
- "VPSRLDQYri",
- "VPSRLDQZ128rr",
- "VPSRLDQZ256rr",
- "VPSRLDQZrr",
- "(V?)PSRLDQri")>;
+ "VMOVDI2PDIrr")>;
def SKXWriteResGroup4 : SchedWriteRes<[SKXPort6]> {
let Latency = 1;
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