[PATCH] D46247: [LLD][ELF][AArch64] Simplify relocations sharing same encoding [NFC]

[Peter Smith via Phabricator via llvm-commits]

peter.smith created this revision.
peter.smith added reviewers: ruiu, espindola.
Herald added subscribers: kristof.beyls, arichardson, emaste, rengolin.
Herald added a reviewer: javed.absar.

The code to encode the result in relocateOne for the relocations:
R_AARCH64_LD64_GOT_LO12_NC
R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
R_AARCH64_TLSDESC_LD64_LO12

      

is equivalent to that for R_AARCH64_LDST64_ABS_LO12_NC. This is described in the ABI as "Set the LD/ST immediate field bits [11:3] of X. No overflow check; check that X&7 =0." This is a simple refactoring change to combine into one case.


https://reviews.llvm.org/D46247

Files:
  ELF/Arch/AArch64.cpp


Index: ELF/Arch/AArch64.cpp
===================================================================
--- ELF/Arch/AArch64.cpp
+++ ELF/Arch/AArch64.cpp
@@ -289,12 +289,6 @@
     checkInt(Loc, Val, 21, Type);
     or32le(Loc, (Val & 0x1FFFFC) << 3);
     break;
-  case R_AARCH64_LD64_GOT_LO12_NC:
-  case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
-  case R_AARCH64_TLSDESC_LD64_LO12:
-    checkAlignment(Loc, Val, 8, Type);
-    or32le(Loc, (Val & 0xFF8) << 7);
-    break;
   case R_AARCH64_LDST8_ABS_LO12_NC:
     or32AArch64Imm(Loc, getBits(Val, 0, 11));
     break;
@@ -307,6 +301,9 @@
     or32AArch64Imm(Loc, getBits(Val, 2, 11));
     break;
   case R_AARCH64_LDST64_ABS_LO12_NC:
+  case R_AARCH64_LD64_GOT_LO12_NC:
+  case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
+  case R_AARCH64_TLSDESC_LD64_LO12:
     checkAlignment(Loc, Val, 8, Type);
     or32AArch64Imm(Loc, getBits(Val, 3, 11));
     break;


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