[llvm] r331161 - [X86] Add a Requires<[In64BitMode]> to FARJMP64

[Craig Topper via llvm-commits]

Author: ctopper
Date: Sun Apr 29 23:21:24 2018
New Revision: 331161

URL: http://llvm.org/viewvc/llvm-project?rev=331161&view=rev
Log:
[X86] Add a Requires<[In64BitMode]> to FARJMP64

Otherwise we can try to assemble it in 32-bit mode and throw an assert in the encoder.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrControl.td
    llvm/trunk/test/MC/X86/intel-syntax.s
    llvm/trunk/test/MC/X86/x86_errors.s

Modified: llvm/trunk/lib/Target/X86/X86InstrControl.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrControl.td?rev=331161&r1=331160&r2=331161&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrControl.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrControl.td Sun Apr 29 23:21:24 2018
@@ -178,7 +178,7 @@ let isBranch = 1, isTerminator = 1, isBa
                             OpSize32, Sched<[WriteJump]>;
   }
   def FARJMP64   : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
-                      "ljmp{q}\t{*}$dst", []>, Sched<[WriteJump]>;
+                      "ljmp{q}\t{*}$dst", []>, Sched<[WriteJump]>, Requires<[In64BitMode]>;
 
   let AsmVariantName = "att" in
   def FARJMP16m  : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),

Modified: llvm/trunk/test/MC/X86/intel-syntax.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/intel-syntax.s?rev=331161&r1=331160&r2=331161&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/intel-syntax.s (original)
+++ llvm/trunk/test/MC/X86/intel-syntax.s Sun Apr 29 23:21:24 2018
@@ -62,7 +62,7 @@ main:
   lcall [rax]
 // CHECK: ljmpl *(%rax)
   jmp FWORD ptr [rax]
-// CHECK: ljmpl *(%rax)
+// CHECK: ljmpq *(%rax)
   ljmp [rax]
 
 // CHECK:	movl	$257, -4(%rsp)

Modified: llvm/trunk/test/MC/X86/x86_errors.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86_errors.s?rev=331161&r1=331160&r2=331161&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86_errors.s (original)
+++ llvm/trunk/test/MC/X86/x86_errors.s Sun Apr 29 23:21:24 2018
@@ -78,3 +78,6 @@ mov %rip, %rax
 // 32: error: register %rax is only available in 64-bit mode
 // 64: error: %rip is not allowed as an index register
 mov (%rax,%rip), %rbx
+
+// 32: error: instruction requires: 64-bit mode
+ljmpq *(%eax)