Author: rksimon
Date: Sun Apr 29 08:33:15 2018
New Revision: 331143
URL: http://llvm.org/viewvc/llvm-project?rev=331143&view=rev
Log:
[X86] Merge more instregex single matches to reduce InstrRW compile time.
Modified:
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=331143&r1=331142&r2=331143&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Sun Apr 29 08:33:15 2018
@@ -450,9 +450,8 @@ def BWWriteResGroup9 : SchedWriteRes<[BW
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[BWWriteResGroup9], (instregex "LAHF", // TODO: This doesnt match Agner's data
- "NOOP",
- "SAHF", // TODO: This doesn't match Agner's data
+def: InstRW<[BWWriteResGroup9], (instrs LAHF, SAHF)>; // TODO: This doesnt match Agner's data
+def: InstRW<[BWWriteResGroup9], (instregex "NOOP",
"SGDT64m",
"SIDT64m",
"SMSW16m",
@@ -884,7 +883,7 @@ def BWWriteResGroup54 : SchedWriteRes<[B
let NumMicroOps = 5;
let ResourceCycles = [1,4];
}
-def: InstRW<[BWWriteResGroup54], (instregex "PAUSE")>;
+def: InstRW<[BWWriteResGroup54], (instrs PAUSE)>;
def BWWriteResGroup55 : SchedWriteRes<[BWPort06,BWPort0156]> {
let Latency = 5;
@@ -1197,24 +1196,15 @@ def BWWriteResGroup81 : SchedWriteRes<[B
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[BWWriteResGroup81], (instregex "PSLLDrm",
- "PSLLQrm",
- "PSLLWrm",
- "PSRADrm",
- "PSRAWrm",
- "PSRLDrm",
- "PSRLQrm",
- "PSRLWrm",
- "PTESTrm",
- "VPSLLDrm",
- "VPSLLQrm",
- "VPSLLWrm",
- "VPSRADrm",
- "VPSRAWrm",
- "VPSRLDrm",
- "VPSRLQrm",
- "VPSRLWrm",
- "VPTESTrm")>;
+def: InstRW<[BWWriteResGroup81], (instregex "(V?)PSLLDrm",
+ "(V?)PSLLQrm",
+ "(V?)PSLLWrm",
+ "(V?)PSRADrm",
+ "(V?)PSRAWrm",
+ "(V?)PSRLDrm",
+ "(V?)PSRLQrm",
+ "(V?)PSRLWrm",
+ "(V?)PTESTrm")>;
def BWWriteResGroup82 : SchedWriteRes<[BWPort0,BWPort01,BWPort23]> {
let Latency = 7;
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=331143&r1=331142&r2=331143&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Sun Apr 29 08:33:15 2018
@@ -450,7 +450,7 @@ def : InstRW<[HWWriteBOUND], (instregex
def HWWriteINTO : SchedWriteRes<[]> {
let NumMicroOps = 4;
}
-def : InstRW<[HWWriteINTO], (instregex "INTO")>;
+def : InstRW<[HWWriteINTO], (instrs INTO)>;
//-- String instructions --//
@@ -1941,7 +1941,7 @@ def HWWriteResGroup99 : SchedWriteRes<[H
let NumMicroOps = 5;
let ResourceCycles = [1,4];
}
-def: InstRW<[HWWriteResGroup99], (instregex "PAUSE")>;
+def: InstRW<[HWWriteResGroup99], (instrs PAUSE)>;
def HWWriteResGroup100 : SchedWriteRes<[HWPort06,HWPort0156]> {
let Latency = 5;
Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=331143&r1=331142&r2=331143&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Sun Apr 29 08:33:15 2018
@@ -375,6 +375,7 @@ def SBWriteResGroup4 : SchedWriteRes<[SB
let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup4], (instrs CDQ, CQO)>;
+def: InstRW<[SBWriteResGroup4], (instrs LAHF, SAHF)>;
def: InstRW<[SBWriteResGroup4], (instregex "BT(16|32|64)ri8",
"BT(16|32|64)rr",
"BTC(16|32|64)ri8",
@@ -383,8 +384,6 @@ def: InstRW<[SBWriteResGroup4], (instreg
"BTR(16|32|64)rr",
"BTS(16|32|64)ri8",
"BTS(16|32|64)rr",
- "LAHF",
- "SAHF",
"VMOVDQA(Y?)rr",
"VMOVDQU(Y?)rr")>;
@@ -712,7 +711,7 @@ def SBWriteResGroup29_2 : SchedWriteRes<
let NumMicroOps = 4;
let ResourceCycles = [1,3];
}
-def: InstRW<[SBWriteResGroup29_2], (instregex "PAUSE")>;
+def: InstRW<[SBWriteResGroup29_2], (instrs PAUSE)>;
def SBWriteResGroup29_3 : SchedWriteRes<[SBPort05,SBPort015]> {
let Latency = 4;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=331143&r1=331142&r2=331143&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Sun Apr 29 08:33:15 2018
@@ -532,11 +532,10 @@ def SKLWriteResGroup10 : SchedWriteRes<[
let ResourceCycles = [1];
}
def: InstRW<[SKLWriteResGroup10], (instrs CBW, CWDE, CDQE)>;
+def: InstRW<[SKLWriteResGroup10], (instrs LAHF, SAHF)>; // TODO: This doesn't match Agner's data
def: InstRW<[SKLWriteResGroup10], (instregex "CLC",
"CMC",
- "LAHF", // TODO: This doesn't match Agner's data
"NOOP",
- "SAHF", // TODO: This doesn't match Agner's data
"SGDT64m",
"SIDT64m",
"SMSW16m",
@@ -978,7 +977,7 @@ def SKLWriteResGroup55 : SchedWriteRes<[
let NumMicroOps = 4;
let ResourceCycles = [1,3];
}
-def: InstRW<[SKLWriteResGroup55], (instregex "PAUSE")>;
+def: InstRW<[SKLWriteResGroup55], (instrs PAUSE)>;
def SKLWriteResGroup56 : SchedWriteRes<[SKLPort015,SKLPort0156]> {
let Latency = 4;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=331143&r1=331142&r2=331143&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Sun Apr 29 08:33:15 2018
@@ -440,8 +440,6 @@ def: InstRW<[SKXWriteResGroup3], (instre
"MMX_MOVD64to64rr",
"MOV64toPQIrr",
"MOVDI2PDIrr",
- "PSLLDQri",
- "PSRLDQri",
"UCOM_FPr",
"UCOM_Fr",
"VMOV64toPQIZrr",
@@ -452,12 +450,12 @@ def: InstRW<[SKXWriteResGroup3], (instre
"VPSLLDQZ128rr",
"VPSLLDQZ256rr",
"VPSLLDQZrr",
- "VPSLLDQri",
+ "(V?)PSLLDQri",
"VPSRLDQYri",
"VPSRLDQZ128rr",
"VPSRLDQZ256rr",
"VPSRLDQZrr",
- "VPSRLDQri")>;
+ "(V?)PSRLDQri")>;
def SKXWriteResGroup4 : SchedWriteRes<[SKXPort6]> {
let Latency = 1;
@@ -471,59 +469,16 @@ def SKXWriteResGroup5 : SchedWriteRes<[S
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKXWriteResGroup5], (instregex "PABSBrr",
- "PABSDrr",
- "PABSWrr",
- "PADDSBrr",
- "PADDSWrr",
- "PADDUSBrr",
- "PADDUSWrr",
- "PAVGBrr",
- "PAVGWrr",
- "PCMPEQBrr",
- "PCMPEQDrr",
- "PCMPEQQrr",
- "PCMPEQWrr",
- "PCMPGTBrr",
- "PCMPGTDrr",
- "PCMPGTWrr",
- "PMAXSBrr",
- "PMAX(C?)SDrr",
- "PMAXSWrr",
- "PMAXUBrr",
- "PMAXUDrr",
- "PMAXUWrr",
- "PMINSBrr",
- "PMIN(C?)SDrr",
- "PMINSWrr",
- "PMINUBrr",
- "PMINUDrr",
- "PMINUWrr",
- "PSIGNBrr",
- "PSIGNDrr",
- "PSIGNWrr",
- "PSLLDri",
- "PSLLQri",
- "PSLLWri",
- "PSRADri",
- "PSRAWri",
- "PSRLDri",
- "PSRLQri",
- "PSRLWri",
- "PSUBSBrr",
- "PSUBSWrr",
- "PSUBUSBrr",
- "PSUBUSWrr",
- "VPABSBYrr",
+def: InstRW<[SKXWriteResGroup5], (instregex "VPABSBYrr",
"VPABSBZ128rr",
"VPABSBZ256rr",
"VPABSBZrr",
- "VPABSBrr",
+ "(V?)PABSBrr",
"VPABSDYrr",
"VPABSDZ128rr",
"VPABSDZ256rr",
"VPABSDZrr",
- "VPABSDrr",
+ "(V?)PABSDrr",
"VPABSQZ128rr",
"VPABSQZ256rr",
"VPABSQZrr",
@@ -531,111 +486,104 @@ def: InstRW<[SKXWriteResGroup5], (instre
"VPABSWZ128rr",
"VPABSWZ256rr",
"VPABSWZrr",
- "VPABSWrr",
+ "(V?)PABSWrr",
"VPADDSBYrr",
"VPADDSBZ128rr",
"VPADDSBZ256rr",
"VPADDSBZrr",
- "VPADDSBrr",
+ "(V?)PADDSBrr",
"VPADDSWYrr",
"VPADDSWZ128rr",
"VPADDSWZ256rr",
"VPADDSWZrr",
- "VPADDSWrr",
+ "(V?)PADDSWrr",
"VPADDUSBYrr",
"VPADDUSBZ128rr",
"VPADDUSBZ256rr",
"VPADDUSBZrr",
- "VPADDUSBrr",
+ "(V?)PADDUSBrr",
"VPADDUSWYrr",
"VPADDUSWZ128rr",
"VPADDUSWZ256rr",
"VPADDUSWZrr",
- "VPADDUSWrr",
+ "(V?)PADDUSWrr",
"VPAVGBYrr",
"VPAVGBZ128rr",
"VPAVGBZ256rr",
"VPAVGBZrr",
- "VPAVGBrr",
+ "(V?)PAVGBrr",
"VPAVGWYrr",
"VPAVGWZ128rr",
"VPAVGWZ256rr",
"VPAVGWZrr",
- "VPAVGWrr",
- "VPCMPEQBYrr",
- "VPCMPEQBrr",
- "VPCMPEQDYrr",
- "VPCMPEQDrr",
- "VPCMPEQQYrr",
- "VPCMPEQQrr",
- "VPCMPEQWYrr",
- "VPCMPEQWrr",
- "VPCMPGTBYrr",
- "VPCMPGTBrr",
- "VPCMPGTDYrr",
- "VPCMPGTDrr",
- "VPCMPGTWYrr",
- "VPCMPGTWrr",
+ "(V?)PAVGWrr",
+ "(V?)PCMPEQB(Y?)rr",
+ "(V?)PCMPEQD(Y?)rr",
+ "(V?)PCMPEQQ(Y?)rr",
+ "(V?)PCMPEQW(Y?)rr",
+ "(V?)PCMPGTB(Y?)rr",
+ "(V?)PCMPGTD(Y?)rr",
+ "(V?)PCMPGTW(Y?)rr",
"VPMAXSBYrr",
"VPMAXSBZ128rr",
"VPMAXSBZ256rr",
"VPMAXSBZrr",
- "VPMAXSBrr",
+ "(V?)PMAXSBrr",
"VPMAX(C?)SDYrr",
"VPMAX(C?)SDZ128rr",
"VPMAX(C?)SDZ256rr",
"VPMAX(C?)SDZrr",
- "VPMAX(C?)SDrr",
+ "(V?)PMAX(C?)SDrr",
"VPMAXSWYrr",
"VPMAXSWZ128rr",
"VPMAXSWZ256rr",
"VPMAXSWZrr",
- "VPMAXSWrr",
+ "(V?)PMAXSWrr",
"VPMAXUBYrr",
"VPMAXUBZ128rr",
"VPMAXUBZ256rr",
"VPMAXUBZrr",
- "VPMAXUBrr",
+ "(V?)PMAXUBrr",
"VPMAXUDYrr",
"VPMAXUDZ128rr",
"VPMAXUDZ256rr",
"VPMAXUDZrr",
- "VPMAXUDrr",
+ "(V?)PMAXUDrr",
"VPMAXUWYrr",
"VPMAXUWZ128rr",
"VPMAXUWZ256rr",
"VPMAXUWZrr",
- "VPMAXUWrr",
+ "(V?)PMAXUWrr",
"VPMINSBYrr",
"VPMINSBZ128rr",
"VPMINSBZ256rr",
"VPMINSBZrr",
- "VPMINSBrr",
+ "(V?)PMINSBrr",
"VPMIN(C?)SDYrr",
"VPMIN(C?)SDZ128rr",
"VPMIN(C?)SDZ256rr",
"VPMIN(C?)SDZrr",
- "VPMIN(C?)SDrr",
+ "(V?)PMIN(C?)SDrr",
"VPMINSWYrr",
"VPMINSWZ128rr",
"VPMINSWZ256rr",
"VPMINSWZrr",
- "VPMINSWrr",
+ "(V?)PMINSWrr",
"VPMINUBYrr",
"VPMINUBZ128rr",
"VPMINUBZ256rr",
"VPMINUBZrr",
- "VPMINUBrr",
+ "(V?)PMINUBrr",
"VPMINUDYrr",
"VPMINUDZ128rr",
"VPMINUDZ256rr",
"VPMINUDZrr",
- "VPMINUDrr",
+ "(V?)PMINUDrr",
"VPMINUWYrr",
"VPMINUWZ128rr",
"VPMINUWZ256rr",
"VPMINUWZrr",
- "VPMINUWrr",
+ "(V?)PMINUWrr",
"VPROLDZ128ri",
"VPROLDZ256ri",
"VPROLDZri",
@@ -660,22 +608,19 @@ def: InstRW<[SKXWriteResGroup5], (instre
"VPRORVQZ128rr",
"VPRORVQZ256rr",
"VPRORVQZrr",
- "VPSIGNBYrr",
- "VPSIGNBrr",
- "VPSIGNDYrr",
- "VPSIGNDrr",
- "VPSIGNWYrr",
- "VPSIGNWrr",
- "VPSLLDYri",
+ "(V?)PSIGNB(Y?)rr",
+ "(V?)PSIGND(Y?)rr",
+ "(V?)PSIGNW(Y?)rr",
+ "(V?)PSLLDYri",
"VPSLLDZ128ri",
"VPSLLDZ256ri",
"VPSLLDZri",
- "VPSLLDri",
+ "(V?)PSLLDri",
"VPSLLQYri",
"VPSLLQZ128ri",
"VPSLLQZ256ri",
"VPSLLQZri",
- "VPSLLQri",
+ "(V?)PSLLQri",
"VPSLLVDYrr",
"VPSLLVDZ128rr",
"VPSLLVDZ256rr",
@@ -693,12 +638,12 @@ def: InstRW<[SKXWriteResGroup5], (instre
"VPSLLWZ128ri",
"VPSLLWZ256ri",
"VPSLLWZri",
- "VPSLLWri",
+ "(V?)PSLLWri",
"VPSRADYri",
"VPSRADZ128ri",
"VPSRADZ256ri",
"VPSRADZri",
- "VPSRADri",
+ "(V?)PSRADri",
"VPSRAQZ128ri",
"VPSRAQZ256ri",
"VPSRAQZri",
@@ -717,17 +662,17 @@ def: InstRW<[SKXWriteResGroup5], (instre
"VPSRAWZ128ri",
"VPSRAWZ256ri",
"VPSRAWZri",
- "VPSRAWri",
+ "(V?)PSRAWri",
"VPSRLDYri",
"VPSRLDZ128ri",
"VPSRLDZ256ri",
"VPSRLDZri",
- "VPSRLDri",
+ "(V?)PSRLDri",
"VPSRLQYri",
"VPSRLQZ128ri",
"VPSRLQZ256ri",
"VPSRLQZri",
- "VPSRLQri",
+ "(V?)PSRLQri",
"VPSRLVDYrr",
"VPSRLVDZ128rr",
"VPSRLVDZ256rr",
@@ -745,27 +690,27 @@ def: InstRW<[SKXWriteResGroup5], (instre
"VPSRLWZ128ri",
"VPSRLWZ256ri",
"VPSRLWZri",
- "VPSRLWri",
+ "(V?)PSRLWri",
"VPSUBSBYrr",
"VPSUBSBZ128rr",
"VPSUBSBZ256rr",
"VPSUBSBZrr",
- "VPSUBSBrr",
+ "(V?)PSUBSBrr",
"VPSUBSWYrr",
"VPSUBSWZ128rr",
"VPSUBSWZ256rr",
"VPSUBSWZrr",
- "VPSUBSWrr",
+ "(V?)PSUBSWrr",
"VPSUBUSBYrr",
"VPSUBUSBZ128rr",
"VPSUBUSBZ256rr",
"VPSUBUSBZrr",
- "VPSUBUSBrr",
+ "(V?)PSUBUSBrr",
"VPSUBUSWYrr",
"VPSUBUSWZ128rr",
"VPSUBUSWZ256rr",
"VPSUBUSWZrr",
- "VPSUBUSWrr")>;
+ "(V?)PSUBUSWrr")>;
def SKXWriteResGroup6 : SchedWriteRes<[SKXPort05]> {
let Latency = 1;
@@ -821,15 +766,7 @@ def SKXWriteResGroup9 : SchedWriteRes<[S
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKXWriteResGroup9], (instregex "PADDBrr",
- "PADDDrr",
- "PADDQrr",
- "PADDWrr",
- "PSUBBrr",
- "PSUBDrr",
- "PSUBQrr",
- "PSUBWrr",
- "VBLENDMPDZ128rr",
+def: InstRW<[SKXWriteResGroup9], (instregex "VBLENDMPDZ128rr",
"VBLENDMPDZ256rr",
"VBLENDMPDZrr",
"VBLENDMPSZ128rr",
@@ -839,22 +776,22 @@ def: InstRW<[SKXWriteResGroup9], (instre
"VPADDBZ128rr",
"VPADDBZ256rr",
"VPADDBZrr",
- "VPADDBrr",
+ "(V?)PADDBrr",
"VPADDDYrr",
"VPADDDZ128rr",
"VPADDDZ256rr",
"VPADDDZrr",
- "VPADDDrr",
+ "(V?)PADDDrr",
"VPADDQYrr",
"VPADDQZ128rr",
"VPADDQZ256rr",
"VPADDQZrr",
- "VPADDQrr",
+ "(V?)PADDQrr",
"VPADDWYrr",
"VPADDWZ128rr",
"VPADDWZ256rr",
"VPADDWZrr",
- "VPADDWrr",
+ "(V?)PADDWrr",
"VPBLENDDYrri",
"VPBLENDDrri",
"VPBLENDMBZ128rr",
@@ -873,21 +810,21 @@ def: InstRW<[SKXWriteResGroup9], (instre
"VPSUBBZ128rr",
"VPSUBBZ256rr",
"VPSUBBZrr",
- "VPSUBBrr",
+ "(V?)PSUBBrr",
"VPSUBDYrr",
"VPSUBDZ128rr",
"VPSUBDZ256rr",
"VPSUBDZrr",
- "VPSUBDrr",
+ "(V?)PSUBDrr",
"VPSUBQYrr",
"VPSUBQZ128rr",
"VPSUBQZ256rr",
"VPSUBQZrr",
- "VPSUBQrr",
+ "(V?)PSUBQrr",
"VPSUBWYrr",
"VPSUBWZ128rr",
"VPSUBWZrr",
- "VPSUBWrr",
+ "(V?)PSUBWrr",
"VPTERNLOGDZ128rri",
"VPTERNLOGDZ256rri",
"VPTERNLOGDZrri",
@@ -901,11 +838,10 @@ def SKXWriteResGroup10 : SchedWriteRes<[
let ResourceCycles = [1];
}
def: InstRW<[SKXWriteResGroup10], (instrs CBW, CWDE, CDQE)>;
+def: InstRW<[SKXWriteResGroup10], (instrs LAHF, SAHF)>; // TODO: This doesn't match Agner's data
def: InstRW<[SKXWriteResGroup10], (instregex "CLC",
"CMC",
- "LAHF", // TODO: This doesn't match Agner's data
"NOOP",
- "SAHF", // TODO: This doesn't match Agner's data
"SGDT64m",
"SIDT64m",
"SMSW16m",
@@ -1112,30 +1048,22 @@ def SKXWriteResGroup19 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKXWriteResGroup19], (instregex "PSLLDrr",
- "PSLLQrr",
- "PSLLWrr",
- "PSRADrr",
- "PSRAWrr",
- "PSRLDrr",
- "PSRLQrr",
- "PSRLWrr",
- "VPSLLDZ128rr",
- "VPSLLDrr",
+def: InstRW<[SKXWriteResGroup19], (instregex "VPSLLDZ128rr",
+ "(V?)PSLLDrr",
"VPSLLQZ128rr",
- "VPSLLQrr",
+ "(V?)PSLLQrr",
"VPSLLWZ128rr",
- "VPSLLWrr",
+ "(V?)PSLLWrr",
"VPSRADZ128rr",
- "VPSRADrr",
+ "(V?)PSRADrr",
"VPSRAQZ128rr",
"VPSRAWZ128rr",
- "VPSRAWrr",
+ "(V?)PSRAWrr",
"VPSRLDZ128rr",
- "VPSRLDrr",
+ "(V?)PSRLDrr",
"VPSRLQZ128rr",
- "VPSRLQrr",
- "VPSRLWrr")>;
+ "(V?)PSRLQrr",
+ "(V?)PSRLWrr")>;
def SKXWriteResGroup20 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
let Latency = 2;
@@ -1268,7 +1196,6 @@ def: InstRW<[SKXWriteResGroup32], (instr
"KUNPCKBWrr",
"KUNPCKDQrr",
"KUNPCKWDrr",
- "PCMPGTQrr",
"VALIGNDZ128rri",
"VALIGNDZ256rri",
"VALIGNDZrri",
@@ -1324,7 +1251,7 @@ def: InstRW<[SKXWriteResGroup32], (instr
"VPCMPGTQZ128rr",
"VPCMPGTQZ256rr",
"VPCMPGTQZrr",
- "VPCMPGTQrr",
+ "(V?)PCMPGTQrr",
"VPCMPGTWZ128rr",
"VPCMPGTWZ256rr",
"VPCMPGTWZrr",
@@ -1481,12 +1408,7 @@ def SKXWriteResGroup38 : SchedWriteRes<[
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[SKXWriteResGroup38], (instregex "PHADDSWrr",
- "PHSUBSWrr",
- "VPHADDSWrr",
- "VPHADDSWYrr",
- "VPHSUBSWrr",
- "VPHSUBSWYrr")>;
+def: InstRW<[SKXWriteResGroup38], (instregex "(V?)PH(ADD|SUB)SW(Y?)rr")>;
def SKXWriteResGroup39 : SchedWriteRes<[SKXPort5,SKXPort05]> {
let Latency = 3;
@@ -1500,18 +1422,7 @@ def SKXWriteResGroup40 : SchedWriteRes<[
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[SKXWriteResGroup40], (instregex "PHADDDrr",
- "PHADDWrr",
- "PHSUBDrr",
- "PHSUBWrr",
- "VPHADDDYrr",
- "VPHADDDrr",
- "VPHADDWYrr",
- "VPHADDWrr",
- "VPHSUBDYrr",
- "VPHSUBDrr",
- "VPHSUBWYrr",
- "VPHSUBWrr")>;
+def: InstRW<[SKXWriteResGroup40], (instregex "(V?)PH(ADD|SUB)(D|W)(Y?)rr")>;
def SKXWriteResGroup41 : SchedWriteRes<[SKXPort5,SKXPort0156]> {
let Latency = 3;
@@ -1595,22 +1506,11 @@ def SKXWriteResGroup50 : SchedWriteRes<[
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKXWriteResGroup50], (instregex "CVTDQ2PSrr",
- "CVTPS2DQrr",
- "CVTTPS2DQrr",
- "PMADDUBSWrr",
- "PMADDWDrr",
- "PMULDQrr",
- "PMULHRSWrr",
- "PMULHUWrr",
- "PMULHWrr",
- "PMULLWrr",
- "PMULUDQrr",
- "VCVTDQ2PSYrr",
+def: InstRW<[SKXWriteResGroup50], (instregex "VCVTDQ2PSYrr",
"VCVTDQ2PSZ128rr",
"VCVTDQ2PSZ256rr",
"VCVTDQ2PSZrr",
- "VCVTDQ2PSrr",
+ "(V?)CVTDQ2PSrr",
"VCVTPD2QQZ128rr",
"VCVTPD2QQZ256rr",
"VCVTPD2QQZrr",
@@ -1621,7 +1521,7 @@ def: InstRW<[SKXWriteResGroup50], (instr
"VCVTPS2DQZ128rr",
"VCVTPS2DQZ256rr",
"VCVTPS2DQZrr",
- "VCVTPS2DQrr",
+ "(V?)CVTPS2DQrr",
"VCVTPS2UDQZ128rr",
"VCVTPS2UDQZ256rr",
"VCVTPS2UDQZrr",
@@ -1638,7 +1538,7 @@ def: InstRW<[SKXWriteResGroup50], (instr
"VCVTTPS2DQZ128rr",
"VCVTTPS2DQZ256rr",
"VCVTTPS2DQZrr",
- "VCVTTPS2DQrr",
+ "(V?)CVTTPS2DQrr",
"VCVTTPS2UDQZ128rr",
"VCVTTPS2UDQZ256rr",
"VCVTTPS2UDQZrr",
@@ -1658,42 +1558,42 @@ def: InstRW<[SKXWriteResGroup50], (instr
"VPMADDUBSWZ128rr",
"VPMADDUBSWZ256rr",
"VPMADDUBSWZrr",
- "VPMADDUBSWrr",
+ "(V?)PMADDUBSWrr",
"VPMADDWDYrr",
"VPMADDWDZ128rr",
"VPMADDWDZ256rr",
"VPMADDWDZrr",
- "VPMADDWDrr",
+ "(V?)PMADDWDrr",
"VPMULDQYrr",
"VPMULDQZ128rr",
"VPMULDQZ256rr",
"VPMULDQZrr",
- "VPMULDQrr",
+ "(V?)PMULDQrr",
"VPMULHRSWYrr",
"VPMULHRSWZ128rr",
"VPMULHRSWZ256rr",
"VPMULHRSWZrr",
- "VPMULHRSWrr",
+ "(V?)PMULHRSWrr",
"VPMULHUWYrr",
"VPMULHUWZ128rr",
"VPMULHUWZ256rr",
"VPMULHUWZrr",
- "VPMULHUWrr",
+ "(V?)PMULHUWrr",
"VPMULHWYrr",
"VPMULHWZ128rr",
"VPMULHWZ256rr",
"VPMULHWZrr",
- "VPMULHWrr",
+ "(V?)PMULHWrr",
"VPMULLWYrr",
"VPMULLWZ128rr",
"VPMULLWZ256rr",
"VPMULLWZrr",
- "VPMULLWrr",
+ "(V?)PMULLWrr",
"VPMULUDQYrr",
"VPMULUDQZ128rr",
"VPMULUDQZ256rr",
"VPMULUDQZrr",
- "VPMULUDQrr")>;
+ "(V?)PMULUDQrr")>;
def SKXWriteResGroup51 : SchedWriteRes<[SKXPort5]> {
let Latency = 4;
@@ -2290,44 +2190,20 @@ def SKXWriteResGroup92 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKXWriteResGroup92], (instregex "INSERTPSrm",
- "PACKSSDWrm",
- "PACKSSWBrm",
- "PACKUSDWrm",
- "PACKUSWBrm",
- "PALIGNRrmi",
- "PSHUFBrm",
- "PSHUFDmi",
- "PSHUFHWmi",
- "PSHUFLWmi",
- "PUNPCKHBWrm",
- "PUNPCKHDQrm",
- "PUNPCKHQDQrm",
- "PUNPCKHWDrm",
- "PUNPCKLBWrm",
- "PUNPCKLDQrm",
- "PUNPCKLQDQrm",
- "PUNPCKLWDrm",
- "SHUFPDrmi",
- "SHUFPSrmi",
- "UNPCKHPDrm",
- "UNPCKHPSrm",
- "UNPCKLPDrm",
- "UNPCKLPSrm",
- "VINSERTPSZrm(b?)",
- "VINSERTPSrm",
+def: InstRW<[SKXWriteResGroup92], (instregex "VINSERTPSZrm(b?)",
+ "(V?)INSERTPSrm",
"VMOVSDZrm(b?)",
"VMOVSSZrm(b?)",
"VPACKSSDWZ128rm(b?)",
- "VPACKSSDWrm",
+ "(V?)PACKSSDWrm",
"VPACKSSWBZ128rm(b?)",
- "VPACKSSWBrm",
+ "(V?)PACKSSWBrm",
"VPACKUSDWZ128rm(b?)",
- "VPACKUSDWrm",
+ "(V?)PACKUSDWrm",
"VPACKUSWBZ128rm(b?)",
- "VPACKUSWBrm",
+ "(V?)PACKUSWBrm",
"VPALIGNRZ128rmi(b?)",
- "VPALIGNRrmi",
+ "(V?)PALIGNRrmi",
"VPBROADCASTBZ128m(b?)",
"VPBROADCASTBrm",
"VPBROADCASTWZ128m(b?)",
@@ -2341,43 +2217,43 @@ def: InstRW<[SKXWriteResGroup92], (instr
"VPERMILPSmi",
"VPERMILPSrm",
"VPSHUFBZ128rm(b?)",
- "VPSHUFBrm",
+ "(V?)PSHUFBrm",
"VPSHUFDZ128m(b?)i",
- "VPSHUFDmi",
+ "(V?)PSHUFDmi",
"VPSHUFHWZ128mi(b?)",
- "VPSHUFHWmi",
+ "(V?)PSHUFHWmi",
"VPSHUFLWZ128mi(b?)",
- "VPSHUFLWmi",
+ "(V?)PSHUFLWmi",
"VPSLLDQZ128rm(b?)",
"VPSRLDQZ128rm(b?)",
"VPUNPCKHBWZ128rm(b?)",
- "VPUNPCKHBWrm",
+ "(V?)PUNPCKHBWrm",
"VPUNPCKHDQZ128rm(b?)",
- "VPUNPCKHDQrm",
+ "(V?)PUNPCKHDQrm",
"VPUNPCKHQDQZ128rm(b?)",
- "VPUNPCKHQDQrm",
+ "(V?)PUNPCKHQDQrm",
"VPUNPCKHWDZ128rm(b?)",
- "VPUNPCKHWDrm",
+ "(V?)PUNPCKHWDrm",
"VPUNPCKLBWZ128rm(b?)",
- "VPUNPCKLBWrm",
+ "(V?)PUNPCKLBWrm",
"VPUNPCKLDQZ128rm(b?)",
- "VPUNPCKLDQrm",
+ "(V?)PUNPCKLDQrm",
"VPUNPCKLQDQZ128rm(b?)",
- "VPUNPCKLQDQrm",
+ "(V?)PUNPCKLQDQrm",
"VPUNPCKLWDZ128rm(b?)",
- "VPUNPCKLWDrm",
+ "(V?)PUNPCKLWDrm",
"VSHUFPDZ128rm(b?)i",
- "VSHUFPDrmi",
+ "(V?)SHUFPDrmi",
"VSHUFPSZ128rm(b?)i",
- "VSHUFPSrmi",
+ "(V?)SHUFPSrmi",
"VUNPCKHPDZ128rm(b?)",
- "VUNPCKHPDrm",
+ "(V?)UNPCKHPDrm",
"VUNPCKHPSZ128rm(b?)",
- "VUNPCKHPSrm",
+ "(V?)UNPCKHPSrm",
"VUNPCKLPDZ128rm(b?)",
- "VUNPCKLPDrm",
+ "(V?)UNPCKLPDrm",
"VUNPCKLPSZ128rm(b?)",
- "VUNPCKLPSrm")>;
+ "(V?)UNPCKLPSrm")>;
def SKXWriteResGroup93 : SchedWriteRes<[SKXPort5,SKXPort015]> {
let Latency = 7;
@@ -2428,99 +2304,56 @@ def SKXWriteResGroup94 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKXWriteResGroup94], (instregex "PABSBrm",
- "PABSDrm",
- "PABSWrm",
- "PADDSBrm",
- "PADDSWrm",
- "PADDUSBrm",
- "PADDUSWrm",
- "PAVGBrm",
- "PAVGWrm",
- "PCMPEQBrm",
- "PCMPEQDrm",
- "PCMPEQQrm",
- "PCMPEQWrm",
- "PCMPGTBrm",
- "PCMPGTDrm",
- "PCMPGTWrm",
- "PMAXSBrm",
- "PMAX(C?)SDrm",
- "PMAXSWrm",
- "PMAXUBrm",
- "PMAXUDrm",
- "PMAXUWrm",
- "PMINSBrm",
- "PMIN(C?)SDrm",
- "PMINSWrm",
- "PMINUBrm",
- "PMINUDrm",
- "PMINUWrm",
- "PSIGNBrm",
- "PSIGNDrm",
- "PSIGNWrm",
- "PSLLDrm",
- "PSLLQrm",
- "PSLLWrm",
- "PSRADrm",
- "PSRAWrm",
- "PSRLDrm",
- "PSRLQrm",
- "PSRLWrm",
- "PSUBSBrm",
- "PSUBSWrm",
- "PSUBUSBrm",
- "PSUBUSWrm",
- "VPABSBZ128rm(b?)",
- "VPABSBrm",
+def: InstRW<[SKXWriteResGroup94], (instregex "VPABSBZ128rm(b?)",
+ "(V?)PABSBrm",
"VPABSDZ128rm(b?)",
- "VPABSDrm",
+ "(V?)PABSDrm",
"VPABSQZ128rm(b?)",
"VPABSWZ128rm(b?)",
- "VPABSWrm",
+ "(V?)PABSWrm",
"VPADDSBZ128rm(b?)",
- "VPADDSBrm",
+ "(V?)PADDSBrm",
"VPADDSWZ128rm(b?)",
- "VPADDSWrm",
+ "(V?)PADDSWrm",
"VPADDUSBZ128rm(b?)",
- "VPADDUSBrm",
+ "(V?)PADDUSBrm",
"VPADDUSWZ128rm(b?)",
- "VPADDUSWrm",
+ "(V?)PADDUSWrm",
"VPAVGBZ128rm(b?)",
- "VPAVGBrm",
+ "(V?)PAVGBrm",
"VPAVGWZ128rm(b?)",
- "VPAVGWrm",
- "VPCMPEQBrm",
- "VPCMPEQDrm",
- "VPCMPEQQrm",
- "VPCMPEQWrm",
- "VPCMPGTBrm",
- "VPCMPGTDrm",
- "VPCMPGTWrm",
+ "(V?)PAVGWrm",
+ "(V?)PCMPEQBrm",
+ "(V?)PCMPEQDrm",
+ "(V?)PCMPEQQrm",
+ "(V?)PCMPEQWrm",
+ "(V?)PCMPGTBrm",
+ "(V?)PCMPGTDrm",
+ "(V?)PCMPGTWrm",
"VPMAXSBZ128rm(b?)",
- "VPMAXSBrm",
+ "(V?)PMAXSBrm",
"VPMAX(C?)SDZ128rm(b?)",
- "VPMAX(C?)SDrm",
+ "(V?)PMAX(C?)SDrm",
"VPMAXSWZ128rm(b?)",
- "VPMAXSWrm",
+ "(V?)PMAXSWrm",
"VPMAXUBZ128rm(b?)",
- "VPMAXUBrm",
+ "(V?)PMAXUBrm",
"VPMAXUDZ128rm(b?)",
- "VPMAXUDrm",
+ "(V?)PMAXUDrm",
"VPMAXUWZ128rm(b?)",
- "VPMAXUWrm",
+ "(V?)PMAXUWrm",
"VPMINSBZ128rm(b?)",
- "VPMINSBrm",
+ "(V?)PMINSBrm",
"VPMIN(C?)SDZ128rm(b?)",
- "VPMIN(C?)SDrm",
+ "(V?)PMIN(C?)SDrm",
"VPMINSWZ128rm(b?)",
- "VPMINSWrm",
+ "(V?)PMINSWrm",
"VPMINUBZ128rm(b?)",
- "VPMINUBrm",
+ "(V?)PMINUBrm",
"VPMINUDZ128rm(b?)",
- "VPMINUDrm",
+ "(V?)PMINUDrm",
"VPMINUWZ128rm(b?)",
- "VPMINUWrm",
+ "(V?)PMINUWrm",
"VPROLDZ128m(b?)i",
"VPROLQZ128m(b?)i",
"VPROLVDZ128rm(b?)",
@@ -2529,15 +2362,15 @@ def: InstRW<[SKXWriteResGroup94], (instr
"VPRORQZ128m(b?)i",
"VPRORVDZ128rm(b?)",
"VPRORVQZ128rm(b?)",
- "VPSIGNBrm",
- "VPSIGNDrm",
- "VPSIGNWrm",
+ "(V?)PSIGNBrm",
+ "(V?)PSIGNDrm",
+ "(V?)PSIGNWrm",
"VPSLLDZ128m(b?)i",
"VPSLLDZ128rm(b?)",
- "VPSLLDrm",
+ "(V?)PSLLDrm",
"VPSLLQZ128m(b?)i",
"VPSLLQZ128rm(b?)",
- "VPSLLQrm",
+ "(V?)PSLLQrm",
"VPSLLVDZ128rm(b?)",
"VPSLLVDrm",
"VPSLLVQZ128rm(b?)",
@@ -2545,10 +2378,10 @@ def: InstRW<[SKXWriteResGroup94], (instr
"VPSLLVWZ128rm(b?)",
"VPSLLWZ128mi(b?)",
"VPSLLWZ128rm(b?)",
- "VPSLLWrm",
+ "(V?)PSLLWrm",
"VPSRADZ128m(b?)i",
"VPSRADZ128rm(b?)",
- "VPSRADrm",
+ "(V?)PSRADrm",
"VPSRAQZ128m(b?)i",
"VPSRAQZ128rm(b?)",
"VPSRAVDZ128rm(b?)",
@@ -2557,13 +2390,13 @@ def: InstRW<[SKXWriteResGroup94], (instr
"VPSRAVWZ128rm(b?)",
"VPSRAWZ128mi(b?)",
"VPSRAWZ128rm(b?)",
- "VPSRAWrm",
+ "(V?)PSRAWrm",
"VPSRLDZ128m(b?)i",
"VPSRLDZ128rm(b?)",
- "VPSRLDrm",
+ "(V?)PSRLDrm",
"VPSRLQZ128m(b?)i",
"VPSRLQZ128rm(b?)",
- "VPSRLQrm",
+ "(V?)PSRLQrm",
"VPSRLVDZ128rm(b?)",
"VPSRLVDrm",
"VPSRLVQZ128rm(b?)",
@@ -2571,30 +2404,22 @@ def: InstRW<[SKXWriteResGroup94], (instr
"VPSRLVWZ128rm(b?)",
"VPSRLWZ128mi(b?)",
"VPSRLWZ128rm(b?)",
- "VPSRLWrm",
+ "(V?)PSRLWrm",
"VPSUBSBZ128rm(b?)",
- "VPSUBSBrm",
+ "(V?)PSUBSBrm",
"VPSUBSWZ128rm(b?)",
- "VPSUBSWrm",
+ "(V?)PSUBSWrm",
"VPSUBUSBZ128rm(b?)",
- "VPSUBUSBrm",
+ "(V?)PSUBUSBrm",
"VPSUBUSWZ128rm(b?)",
- "VPSUBUSWrm")>;
+ "(V?)PSUBUSWrm")>;
def SKXWriteResGroup95 : SchedWriteRes<[SKXPort23,SKXPort015]> {
let Latency = 7;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKXWriteResGroup95], (instregex "PADDBrm",
- "PADDDrm",
- "PADDQrm",
- "PADDWrm",
- "PSUBBrm",
- "PSUBDrm",
- "PSUBQrm",
- "PSUBWrm",
- "VBLENDMPDZ128rm(b?)",
+def: InstRW<[SKXWriteResGroup95], (instregex "VBLENDMPDZ128rm(b?)",
"VBLENDMPSZ128rm(b?)",
"VBROADCASTI32X2Z128m(b?)",
"VBROADCASTSSZ128m(b?)",
@@ -2617,13 +2442,13 @@ def: InstRW<[SKXWriteResGroup95], (instr
"VMOVUPDZ128rm(b?)",
"VMOVUPSZ128rm(b?)",
"VPADDBZ128rm(b?)",
- "VPADDBrm",
+ "(V?)PADDBrm",
"VPADDDZ128rm(b?)",
- "VPADDDrm",
+ "(V?)PADDDrm",
"VPADDQZ128rm(b?)",
- "VPADDQrm",
+ "(V?)PADDQrm",
"VPADDWZ128rm(b?)",
- "VPADDWrm",
+ "(V?)PADDWrm",
"VPBLENDDrmi",
"VPBLENDMBZ128rm(b?)",
"VPBLENDMDZ128rm(b?)",
@@ -2635,13 +2460,13 @@ def: InstRW<[SKXWriteResGroup95], (instr
"VPMASKMOVQrm",
"VPORrm",
"VPSUBBZ128rm(b?)",
- "VPSUBBrm",
+ "(V?)PSUBBrm",
"VPSUBDZ128rm(b?)",
- "VPSUBDrm",
+ "(V?)PSUBDrm",
"VPSUBQZ128rm(b?)",
- "VPSUBQrm",
+ "(V?)PSUBQrm",
"VPSUBWZ128rm(b?)",
- "VPSUBWrm",
+ "(V?)PSUBWrm",
"VPTERNLOGDZ128rm(b?)i",
"VPTERNLOGQZ128rm(b?)i")>;
@@ -2812,11 +2637,7 @@ def SKXWriteResGroup116 : SchedWriteRes<
let NumMicroOps = 2;
let ResourceCycles = [2];
}
-def: InstRW<[SKXWriteResGroup116], (instregex "ROUNDPDr",
- "ROUNDPSr",
- "ROUNDSDr",
- "ROUNDSSr",
- "VRNDSCALEPDZ128rri",
+def: InstRW<[SKXWriteResGroup116], (instregex "VRNDSCALEPDZ128rri",
"VRNDSCALEPDZ256rri",
"VRNDSCALEPDZrri",
"VRNDSCALEPSZ128rri",
@@ -2824,12 +2645,10 @@ def: InstRW<[SKXWriteResGroup116], (inst
"VRNDSCALEPSZrri",
"VRNDSCALESDr",
"VRNDSCALESSr",
- "VROUNDPDr",
- "VROUNDPSr",
- "VROUNDSDr",
- "VROUNDSSr",
- "VROUNDPDYr",
- "VROUNDPSYr")>;
+ "(V?)ROUNDPD(Y?)r",
+ "(V?)ROUNDPS(Y?)r",
+ "(V?)ROUNDSDr",
+ "(V?)ROUNDSSr")>;
def SKXWriteResGroup117 : SchedWriteRes<[SKXPort0,SKXPort23]> {
let Latency = 8;
@@ -3394,8 +3213,7 @@ def SKXWriteResGroup136 : SchedWriteRes<
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKXWriteResGroup136], (instregex "PCMPGTQrm",
- "VALIGNDZ128rm(b?)i",
+def: InstRW<[SKXWriteResGroup136], (instregex "VALIGNDZ128rm(b?)i",
"VALIGNQZ128rm(b?)i",
"VCMPPDZ128rm(b?)i",
"VCMPPSZ128rm(b?)i",
@@ -3412,7 +3230,7 @@ def: InstRW<[SKXWriteResGroup136], (inst
"VPCMPGTBZ128rm(b?)",
"VPCMPGTDZ128rm(b?)",
"VPCMPGTQZ128rm(b?)",
- "VPCMPGTQrm",
+ "(V?)PCMPGTQrm",
"VPCMPGTWZ128rm(b?)",
"VPCMPQZ128rmi(b?)",
"VPCMPUBZ128rmi(b?)",
@@ -4222,18 +4040,14 @@ def SKXWriteResGroup186 : SchedWriteRes<
let NumMicroOps = 3;
let ResourceCycles = [1,2];
}
-def: InstRW<[SKXWriteResGroup186], (instregex "ROUNDPDm",
- "ROUNDPSm",
- "ROUNDSDm",
- "ROUNDSSm",
- "VRNDSCALEPDZ128rm(b?)i",
+def: InstRW<[SKXWriteResGroup186], (instregex "VRNDSCALEPDZ128rm(b?)i",
"VRNDSCALEPSZ128rm(b?)i",
"VRNDSCALESDm(b?)",
"VRNDSCALESSm(b?)",
- "VROUNDPDm",
- "VROUNDPSm",
- "VROUNDSDm",
- "VROUNDSSm")>;
+ "(V?)ROUNDPDm",
+ "(V?)ROUNDPSm",
+ "(V?)ROUNDSDm",
+ "(V?)ROUNDSSm")>;
def SKXWriteResGroup187 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
let Latency = 14;
@@ -4874,5 +4688,5 @@ def SKXWriteResGroup267 : SchedWriteRes<
let NumMicroOps = 4;
let ResourceCycles = [1,3];
}
-def: InstRW<[SKXWriteResGroup267], (instregex "PAUSE")>;
+def: InstRW<[SKXWriteResGroup267], (instrs PAUSE)>;
} // SchedModel
Modified: llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td?rev=331143&r1=331142&r2=331143&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td Sun Apr 29 08:33:15 2018
@@ -361,14 +361,14 @@ def ZnWritePushA : SchedWriteRes<[ZnAGU]
def : InstRW<[ZnWritePushA], (instregex "PUSHA(16|32)")>;
//LAHF
-def : InstRW<[WriteMicrocoded], (instregex "LAHF")>;
+def : InstRW<[WriteMicrocoded], (instrs LAHF)>;
// SAHF.
def ZnWriteSAHF : SchedWriteRes<[ZnALU]> {
let Latency = 2;
let NumMicroOps = 2;
}
-def : InstRW<[ZnWriteSAHF], (instregex "SAHF")>;
+def : InstRW<[ZnWriteSAHF], (instrs SAHF)>;
// BSWAP.
def ZnWriteBSwap : SchedWriteRes<[ZnALU]> {
@@ -513,7 +513,7 @@ def ZnWriteJCXZ : SchedWriteRes<[ZnALU03
def : InstRW<[ZnWriteJCXZ], (instrs JCXZ, JECXZ, JRCXZ)>;
// INTO
-def : InstRW<[WriteMicrocoded], (instregex "INTO")>;
+def : InstRW<[WriteMicrocoded], (instrs INTO)>;
// LOOP.
def ZnWriteLOOP : SchedWriteRes<[ZnALU03]>;
@@ -634,7 +634,7 @@ def ZnWriteLEAVE : SchedWriteRes<[ZnALU,
def : InstRW<[ZnWriteLEAVE], (instregex "LEAVE")>;
// PAUSE.
-def : InstRW<[WriteMicrocoded], (instregex "PAUSE")>;
+def : InstRW<[WriteMicrocoded], (instrs PAUSE)>;
// RDTSC.
def : InstRW<[WriteMicrocoded], (instregex "RDTSC")>;
@@ -1308,7 +1308,7 @@ def : InstRW<[ZnWriteCVTPS2PIr], (instre
// CVTPI2PD.
// x,mm.
-def : InstRW<[ZnWriteCVTPS2PDr], (instregex "MMX_CVT(T?)PI2PDirr")>;
+def : InstRW<[ZnWriteCVTPS2PDr], (instregex "MMX_CVTPI2PDirr")>;
// CVT(T)PD2PI.
// mm,x.