[llvm] r331135 - [X86] Remove SLDT64m instruction.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Apr 28 21:50:53 PDT 2018
Author: ctopper
Date: Sat Apr 28 21:50:53 2018
New Revision: 331135
URL: http://llvm.org/viewvc/llvm-project?rev=331135&view=rev
Log:
[X86] Remove SLDT64m instruction.
It doesn't really exist. The instruction always writes 16-bits of memory. Putting a REX.w on it won't change anything.
While I was touching the encoding tests to remove it, I added some other missing register form test cases.
Modified:
llvm/trunk/lib/Target/X86/X86InstrSystem.td
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
llvm/trunk/test/MC/X86/I286-32.s
llvm/trunk/test/MC/X86/I286-64.s
Modified: llvm/trunk/lib/Target/X86/X86InstrSystem.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSystem.td?rev=331135&r1=331134&r2=331135&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSystem.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSystem.td Sat Apr 28 21:50:53 2018
@@ -382,9 +382,6 @@ def SLDT32r : I<0x00, MRM0r, (outs GR32:
// extension.
def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
"sldt{q}\t$dst", []>, TB, Requires<[In64BitMode]>;
-let mayStore = 1 in
-def SLDT64m : RI<0x00, MRM0m, (outs), (ins i16mem:$dst),
- "sldt{q}\t$dst", []>, TB, Requires<[In64BitMode]>;
def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
"lgdt{w}\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>;
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=331135&r1=331134&r2=331135&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Sat Apr 28 21:50:53 2018
@@ -455,7 +455,6 @@ def: InstRW<[BWWriteResGroup9], (instreg
"SAHF", // TODO: This doesn't match Agner's data
"SGDT64m",
"SIDT64m",
- "SLDT64m",
"SMSW16m",
"STRm",
"SYSCALL")>;
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=331135&r1=331134&r2=331135&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Sat Apr 28 21:50:53 2018
@@ -786,7 +786,6 @@ def: InstRW<[HWWriteResGroup10], (instre
"NOOP",
"SGDT64m",
"SIDT64m",
- "SLDT64m",
"SMSW16m",
"STC",
"STRm",
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=331135&r1=331134&r2=331135&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Sat Apr 28 21:50:53 2018
@@ -539,7 +539,6 @@ def: InstRW<[SKLWriteResGroup10], (instr
"SAHF", // TODO: This doesn't match Agner's data
"SGDT64m",
"SIDT64m",
- "SLDT64m",
"SMSW16m",
"STC",
"STRm",
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=331135&r1=331134&r2=331135&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Sat Apr 28 21:50:53 2018
@@ -908,7 +908,6 @@ def: InstRW<[SKXWriteResGroup10], (instr
"SAHF", // TODO: This doesn't match Agner's data
"SGDT64m",
"SIDT64m",
- "SLDT64m",
"SMSW16m",
"STC",
"STRm",
Modified: llvm/trunk/test/MC/X86/I286-32.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/I286-32.s?rev=331135&r1=331134&r2=331135&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/I286-32.s (original)
+++ llvm/trunk/test/MC/X86/I286-32.s Sat Apr 28 21:50:53 2018
@@ -132,6 +132,10 @@ ltrw 64(%edx,%eax)
// CHECK: encoding: [0x0f,0x00,0x1a]
ltrw (%edx)
+// CHECK: sldtw %ax
+// CHECK: encoding: [0x66,0x0f,0x00,0xc0]
+sldtw %ax
+
// CHECK: sldtl %eax
// CHECK: encoding: [0x0f,0x00,0xc0]
sldtl %eax
Modified: llvm/trunk/test/MC/X86/I286-64.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/I286-64.s?rev=331135&r1=331134&r2=331135&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/I286-64.s (original)
+++ llvm/trunk/test/MC/X86/I286-64.s Sat Apr 28 21:50:53 2018
@@ -240,33 +240,17 @@ sidtq 64(%rdx,%rax)
// CHECK: encoding: [0x0f,0x01,0x0a]
sidtq (%rdx)
+// CHECK: sldtw %r13w
+// CHECK: encoding: [0x66,0x41,0x0f,0x00,0xc5]
+sldtw %r13w
+
// CHECK: sldtl %r13d
// CHECK: encoding: [0x41,0x0f,0x00,0xc5]
sldtl %r13d
-// CHECK: sldtq 485498096
-// CHECK: encoding: [0x48,0x0f,0x00,0x04,0x25,0xf0,0x1c,0xf0,0x1c]
-sldtq 485498096
-
-// CHECK: sldtq 64(%rdx)
-// CHECK: encoding: [0x48,0x0f,0x00,0x42,0x40]
-sldtq 64(%rdx)
-
-// CHECK: sldtq 64(%rdx,%rax,4)
-// CHECK: encoding: [0x48,0x0f,0x00,0x44,0x82,0x40]
-sldtq 64(%rdx,%rax,4)
-
-// CHECK: sldtq -64(%rdx,%rax,4)
-// CHECK: encoding: [0x48,0x0f,0x00,0x44,0x82,0xc0]
-sldtq -64(%rdx,%rax,4)
-
-// CHECK: sldtq 64(%rdx,%rax)
-// CHECK: encoding: [0x48,0x0f,0x00,0x44,0x02,0x40]
-sldtq 64(%rdx,%rax)
-
-// CHECK: sldtq (%rdx)
-// CHECK: encoding: [0x48,0x0f,0x00,0x02]
-sldtq (%rdx)
+// CHECK: sldtq %r13
+// CHECK: encoding: [0x49,0x0f,0x00,0xc5]
+sldtq %r13
// CHECK: sldtw 485498096
// CHECK: encoding: [0x0f,0x00,0x04,0x25,0xf0,0x1c,0xf0,0x1c]
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