[llvm] r331110 - [X86] Remove unnecessary shift/rotate folded InstRW overrides.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sat Apr 28 08:32:19 PDT 2018
Author: rksimon
Date: Sat Apr 28 08:32:19 2018
New Revision: 331110
URL: http://llvm.org/viewvc/llvm-project?rev=331110&view=rev
Log:
[X86] Remove unnecessary shift/rotate folded InstRW overrides.
Modified:
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=331110&r1=331109&r2=331110&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Sat Apr 28 08:32:19 2018
@@ -754,13 +754,7 @@ def: InstRW<[HWWriteResGroup7], (instreg
"BTR(16|32|64)ri8",
"BTR(16|32|64)rr",
"BTS(16|32|64)ri8",
- "BTS(16|32|64)rr",
- "SAR(8|16|32|64)r1",
- "SAR(8|16|32|64)ri",
- "SHL(8|16|32|64)r1",
- "SHL(8|16|32|64)ri",
- "SHR(8|16|32|64)r1",
- "SHR(8|16|32|64)ri")>;
+ "BTS(16|32|64)rr")>;
def HWWriteResGroup8 : SchedWriteRes<[HWPort15]> {
let Latency = 1;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=331110&r1=331109&r2=331110&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Sat Apr 28 08:32:19 2018
@@ -497,15 +497,9 @@ def: InstRW<[SKLWriteResGroup7], (instre
"BTR(16|32|64)rr",
"BTS(16|32|64)ri8",
"BTS(16|32|64)rr",
- "SAR(8|16|32|64)r1",
- "SAR(8|16|32|64)ri",
"SBB(16|32|64)ri",
"SBB(16|32|64)i",
- "SBB(8|16|32|64)rr",
- "SHL(8|16|32|64)r1",
- "SHL(8|16|32|64)ri",
- "SHR(8|16|32|64)r1",
- "SHR(8|16|32|64)ri")>;
+ "SBB(8|16|32|64)rr")>;
def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> {
let Latency = 1;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=331110&r1=331109&r2=331110&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Sat Apr 28 08:32:19 2018
@@ -802,15 +802,9 @@ def: InstRW<[SKXWriteResGroup7], (instre
"BTR(16|32|64)rr",
"BTS(16|32|64)ri8",
"BTS(16|32|64)rr",
- "SAR(8|16|32|64)r1",
- "SAR(8|16|32|64)ri",
"SBB(16|32|64)ri",
"SBB(16|32|64)i",
- "SBB(8|16|32|64)rr",
- "SHL(8|16|32|64)r1",
- "SHL(8|16|32|64)ri",
- "SHR(8|16|32|64)r1",
- "SHR(8|16|32|64)ri")>;
+ "SBB(8|16|32|64)rr")>;
def SKXWriteResGroup8 : SchedWriteRes<[SKXPort15]> {
let Latency = 1;
Modified: llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td?rev=331110&r1=331109&r2=331110&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td Sat Apr 28 08:32:19 2018
@@ -622,9 +622,6 @@ def : InstRW<[WriteMicrocoded], (instreg
def : InstRW<[WriteShiftLd], (instregex "S(A|H)(R|L)(8|16|32|64)m(i|1)")>;
// SHRD SHLD.
-// r,r
-def : InstRW<[WriteShift], (instregex "SH(R|L)D(16|32|64)rri8")>;
-
// m,r
def : InstRW<[WriteShiftLd], (instregex "SH(R|L)D(16|32|64)mri8")>;
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