[PATCH] D46221: [RISCV] Lower tail pseudo instruction

Mandeep Singh Grang via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Apr 27 17:12:52 PDT 2018


mgrang created this revision.
mgrang added reviewers: asb, apazos.
Herald added subscribers: edward-jones, zzheng, shiva0217, kito-cheng, niosHD, sabuasal, jordy.potman.lists, simoncook, johnrusso, rbar.
mgrang added a dependency: D45395: [RISCV] Implement tail call optimization.
mgrang added a comment.

Here's the patch to generate tail pseudo instruction: https://reviews.llvm.org/D46221


The tail pseudo instruction is lowered as auipc and jalr.


Repository:
  rL LLVM

https://reviews.llvm.org/D46221

Files:
  lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
  test/MC/RISCV/tail-call-invalid.s
  test/MC/RISCV/tail-call.s

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D46221.144424.patch
Type: text/x-patch
Size: 4783 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180428/3690033a/attachment.bin>


More information about the llvm-commits mailing list