[PATCH] D46161: [DAGCombiner] Fix a case of 1 in non-splat vector pow2 divisor

[Heejin Ahn via Phabricator via llvm-commits]

aheejin created this revision.
aheejin added reviewers: zvi, RKSimon.
Herald added subscribers: llvm-commits, jgravelle-google, sbc100, dschuff, jfb.

https://reviews.llvm.org/D42479 (https://reviews.llvm.org/rL329525) enabled SDIV combine for pow2 non-splat vector
dividers. But when there is a 1 in a vector, the instruction sequence to
be generated involves shifting a value by the number of its bit widths,
which is undefined
(https://github.com/llvm-mirror/llvm/blob/c64f4dbfe31e509f9c1092b951e524b056245af8/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L6000-L6006).

Especially, in architectures that do not support vector instructions,
each of element in a vector will be computed separately using scalar
operations, and then the resulting value will be undef for '1' values
in a vector.

(All 1's vector is fine; only vectors mixed with 1 and others will be
affected.)


Repository:
  rL LLVM

https://reviews.llvm.org/D46161

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/WebAssembly/vector_sdiv.ll
  test/CodeGen/X86/combine-sdiv.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D46161.144252.patch
Type: text/x-patch
Size: 214301 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180427/4b239af2/attachment-0001.bin>