[PATCH] D46156: [DAGCombiner] Change the SDLoc on split extloads (2/N)

[Vedant Kumar via Phabricator via llvm-commits]

vsk created this revision.
vsk added reviewers: niravd, aprantl.

In DAGCombiner, we try to simplify this pattern:

  ([s|z]ext (load ...))

Conceptually, a new extload which is created while splitting the load
should have the same debug location as the load.

Making this change affects the IROrder of the new load, causing some
test case churn.

In practice, the new location never appears to be different from the
location of the [s|z]ext, at least not during check-llvm or a stage2
build.

Part of: llvm.org/PR37262


https://reviews.llvm.org/D46156

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/X86/avg.ll
  test/CodeGen/X86/known-signbits-vector.ll
  test/CodeGen/X86/madd.ll
  test/CodeGen/X86/pmovsx-inreg.ll
  test/CodeGen/X86/vec_int_to_fp.ll
  test/CodeGen/X86/vector-sext.ll
  test/CodeGen/X86/vector-zext.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D46156.144246.patch
Type: text/x-patch
Size: 35089 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180427/e321bb06/attachment-0001.bin>