[PATCH] D45995: [DAGCombiner] Set the right SDLoc on a newly-created zextload (1/N)

[Vedant Kumar via Phabricator via llvm-commits]

vsk updated this revision to Diff 144242.
vsk marked 4 inline comments as done.
vsk retitled this revision from "[DAGCombiner] Set the right SDLoc on a newly-created zextload" to "[DAGCombiner] Set the right SDLoc on a newly-created zextload (1/N)".
vsk edited the summary of this revision.
vsk added a comment.

@niravd I'm still working through your comments. Because each change introduces some test case churn, I've split things up for easier review. I'll link the new reviews to this llvm.org/PR37262.

In https://reviews.llvm.org/D45995#1077261, @aprantl wrote:

> Are those extra pushes spills? I could imagine that changing the order of instruction affects register allocation and sufficiently increases the register pressure on i386 (which doesn't have many general purpose registers) to push it over the edge.


I think so. The affected registers are immediately used and subsequently popped.


https://reviews.llvm.org/D45995

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/AArch64/arm64-aapcs.ll
  test/CodeGen/AArch64/arm64-ldp-cluster.ll
  test/CodeGen/ARM/vector-load.ll
  test/CodeGen/X86/avg.ll
  test/CodeGen/X86/dagcombine-cse.ll
  test/CodeGen/X86/fold-zext-trunc.ll
  test/CodeGen/X86/known-bits-vector.ll
  test/CodeGen/X86/legalize-shift-64.ll
  test/CodeGen/X86/load-combine.ll
  test/CodeGen/X86/mulx32.ll
  test/CodeGen/X86/promote-vec3.ll
  test/CodeGen/X86/widen_conv-3.ll
  test/CodeGen/X86/widen_conv-4.ll
  test/CodeGen/X86/win-smallparams.ll

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