[PATCH] D46124: [AArch64][SVE] Asm: Improve diagnostics for gather loads.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen created this revision.
sdesmalen added reviewers: fhahn, rengolin, samparker, SjoerdMeijer.
Herald added a reviewer: javed.absar.
Herald added subscribers: kristof.beyls, tschuett.

This patch extends the 'isSVEVectorRegWithShiftExtend' function to 
improve diagnostics for SVE's gather load (scalar + vector) addressing 
modes. Instead of always suggesting the 'unscaled' addressing mode, 
the use of DiagnosticPredicate enables a more specific error message
in the context where the scaling is incorrect. For example:

  ld1h z0.d, p0/z, [x0, z0.d, lsl #2]
                                   ^ 
           shift amount should be '1'

Instead of suggesting the packed, unscaled addressing mode:

  expected 'z[0..31].d, (uxtw|sxtw)'

the assembler now suggests using the proper scaling:

  expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'


https://reviews.llvm.org/D46124

Files:
  lib/Target/AArch64/AArch64RegisterInfo.td
  lib/Target/AArch64/AArch64SVEInstrInfo.td
  lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  test/MC/AArch64/SVE/ld1d-diagnostics.s
  test/MC/AArch64/SVE/ld1h-diagnostics.s
  test/MC/AArch64/SVE/ld1sh-diagnostics.s
  test/MC/AArch64/SVE/ld1sw-diagnostics.s
  test/MC/AArch64/SVE/ld1w-diagnostics.s
  test/MC/AArch64/SVE/ldff1d-diagnostics.s
  test/MC/AArch64/SVE/ldff1h-diagnostics.s
  test/MC/AArch64/SVE/ldff1sh-diagnostics.s
  test/MC/AArch64/SVE/ldff1sw-diagnostics.s
  test/MC/AArch64/SVE/ldff1w-diagnostics.s

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