[llvm] r330937 - [RISCV] Implement isLegalAddImmediate

[Alex Bradbury via llvm-commits]

Author: asb
Date: Thu Apr 26 06:00:37 2018
New Revision: 330937

URL: http://llvm.org/viewvc/llvm-project?rev=330937&view=rev
Log:
[RISCV] Implement isLegalAddImmediate

This causes a trivial improvement in the recently added lsr-legaladdimm.ll 
test case.

Modified:
    llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h
    llvm/trunk/test/CodeGen/RISCV/lsr-legaladdimm.ll

Modified: llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp?rev=330937&r1=330936&r2=330937&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp Thu Apr 26 06:00:37 2018
@@ -183,6 +183,10 @@ bool RISCVTargetLowering::isLegalAddress
   return true;
 }
 
+bool RISCVTargetLowering::isLegalAddImmediate(int64_t Imm) const {
+  return isInt<12>(Imm);
+}
+
 // Changes the condition code and swaps operands if necessary, so the SetCC
 // operation matches one of the comparisons supported directly in the RISC-V
 // ISA.

Modified: llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h?rev=330937&r1=330936&r2=330937&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h Thu Apr 26 06:00:37 2018
@@ -42,6 +42,7 @@ public:
   bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
                              unsigned AS,
                              Instruction *I = nullptr) const override;
+  bool isLegalAddImmediate(int64_t Imm) const override;
 
   // Provide custom lowering hooks for some operations.
   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;

Modified: llvm/trunk/test/CodeGen/RISCV/lsr-legaladdimm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/lsr-legaladdimm.ll?rev=330937&r1=330936&r2=330937&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/lsr-legaladdimm.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/lsr-legaladdimm.ll Thu Apr 26 06:00:37 2018
@@ -11,22 +11,21 @@
 define i32 @main() nounwind {
 ; RV32I-LABEL: main:
 ; RV32I:       # %bb.0: # %entry
-; RV32I-NEXT:    addi a0, zero, -2048
-; RV32I-NEXT:    lui a1, %hi(b)
-; RV32I-NEXT:    addi a1, a1, %lo(b)
-; RV32I-NEXT:    lui a2, %hi(a)
-; RV32I-NEXT:    addi a2, a2, %lo(a)
-; RV32I-NEXT:    lui a3, 1
-; RV32I-NEXT:    addi a3, a3, -2048
+; RV32I-NEXT:    lui a0, %hi(b)
+; RV32I-NEXT:    addi a0, a0, %lo(b)
+; RV32I-NEXT:    lui a1, %hi(a)
+; RV32I-NEXT:    addi a1, a1, %lo(a)
+; RV32I-NEXT:    lui a2, 1
+; RV32I-NEXT:    mv a3, zero
 ; RV32I-NEXT:  .LBB0_1: # %for.body
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    sw a0, 0(a2)
-; RV32I-NEXT:    add a4, a0, a3
+; RV32I-NEXT:    addi a4, a3, -2048
 ; RV32I-NEXT:    sw a4, 0(a1)
-; RV32I-NEXT:    addi a2, a2, 4
 ; RV32I-NEXT:    addi a1, a1, 4
-; RV32I-NEXT:    addi a0, a0, 1
-; RV32I-NEXT:    bne a0, a3, .LBB0_1
+; RV32I-NEXT:    sw a3, 0(a0)
+; RV32I-NEXT:    addi a0, a0, 4
+; RV32I-NEXT:    addi a3, a3, 1
+; RV32I-NEXT:    bne a3, a2, .LBB0_1
 ; RV32I-NEXT:  # %bb.2: # %for.end
 ; RV32I-NEXT:    mv a0, zero
 ; RV32I-NEXT:    ret