[llvm] r330859 - [MIR] Add support for debug metadata for fixed stack objects

Francis Visoiu Mistrih via llvm-commits llvm-commits at lists.llvm.org
Wed Apr 25 11:58:06 PDT 2018


Author: thegameg
Date: Wed Apr 25 11:58:06 2018
New Revision: 330859

URL: http://llvm.org/viewvc/llvm-project?rev=330859&view=rev
Log:
[MIR] Add support for debug metadata for fixed stack objects

Debug var, expr and loc were only supported for non-fixed stack objects.

This patch adds the following fields to the "fixedStack:" entries, and
renames the ones from "stack:" to:

* debug-info-variable
* debug-info-expression
* debug-info-location

Differential Revision: https://reviews.llvm.org/D46032

Added:
    llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-di.mir
    llvm/trunk/test/CodeGen/X86/fixed-stack-di-mir.ll
Modified:
    llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h
    llvm/trunk/include/llvm/CodeGen/MachineFunction.h
    llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp
    llvm/trunk/lib/CodeGen/MIRPrinter.cpp
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/debug-insts.ll
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/fp128-legalize-crash-pr35690.mir
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-large.mir
    llvm/trunk/test/CodeGen/AArch64/reverse-csr-restore-seq.mir
    llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir
    llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir
    llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir
    llvm/trunk/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
    llvm/trunk/test/CodeGen/AMDGPU/twoaddr-mad.mir
    llvm/trunk/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir
    llvm/trunk/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir
    llvm/trunk/test/CodeGen/ARM/fp16-litpool2-arm.mir
    llvm/trunk/test/CodeGen/ARM/fp16-litpool3-arm.mir
    llvm/trunk/test/CodeGen/MIR/AArch64/mirCanonCopyCopyProp.mir
    llvm/trunk/test/CodeGen/MIR/AArch64/mirCanonIdempotent.mir
    llvm/trunk/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir
    llvm/trunk/test/CodeGen/MIR/X86/callee-saved-info.mir
    llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir
    llvm/trunk/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir
    llvm/trunk/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir
    llvm/trunk/test/CodeGen/MIR/X86/stack-object-debug-info.mir
    llvm/trunk/test/CodeGen/MIR/X86/stack-objects.mir
    llvm/trunk/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir
    llvm/trunk/test/CodeGen/Mips/micromips-eva.mir
    llvm/trunk/test/CodeGen/Mips/micromips-short-delay-slot.mir
    llvm/trunk/test/CodeGen/Mips/msa/emergency-spill.mir
    llvm/trunk/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
    llvm/trunk/test/CodeGen/X86/GlobalISel/x32-select-frameIndex.mir
    llvm/trunk/test/CodeGen/X86/GlobalISel/x86-select-frameIndex.mir
    llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-select-frameIndex.mir
    llvm/trunk/test/CodeGen/X86/movtopush.mir
    llvm/trunk/test/CodeGen/X86/pr30821.mir
    llvm/trunk/test/DebugInfo/MIR/AArch64/implicit-def-dead-scope.mir
    llvm/trunk/test/DebugInfo/MIR/Mips/last-inst-bundled.mir
    llvm/trunk/test/DebugInfo/MIR/X86/kill-after-spill.mir
    llvm/trunk/test/DebugInfo/X86/live-debug-vars-dse.mir

Modified: llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h Wed Apr 25 11:58:06 2018
@@ -258,11 +258,11 @@ template <> struct MappingTraits<Machine
     YamlIO.mapOptional("callee-saved-restored", Object.CalleeSavedRestored,
                        true);
     YamlIO.mapOptional("local-offset", Object.LocalOffset, Optional<int64_t>());
-    YamlIO.mapOptional("di-variable", Object.DebugVar,
+    YamlIO.mapOptional("debug-info-variable", Object.DebugVar,
                        StringValue()); // Don't print it out when it's empty.
-    YamlIO.mapOptional("di-expression", Object.DebugExpr,
+    YamlIO.mapOptional("debug-info-expression", Object.DebugExpr,
                        StringValue()); // Don't print it out when it's empty.
-    YamlIO.mapOptional("di-location", Object.DebugLoc,
+    YamlIO.mapOptional("debug-info-location", Object.DebugLoc,
                        StringValue()); // Don't print it out when it's empty.
   }
 
@@ -283,6 +283,9 @@ struct FixedMachineStackObject {
   bool IsAliased = false;
   StringValue CalleeSavedRegister;
   bool CalleeSavedRestored = true;
+  StringValue DebugVar;
+  StringValue DebugExpr;
+  StringValue DebugLoc;
 
   bool operator==(const FixedMachineStackObject &Other) const {
     return ID == Other.ID && Type == Other.Type && Offset == Other.Offset &&
@@ -290,7 +293,9 @@ struct FixedMachineStackObject {
            StackID == Other.StackID &&
            IsImmutable == Other.IsImmutable && IsAliased == Other.IsAliased &&
            CalleeSavedRegister == Other.CalleeSavedRegister &&
-           CalleeSavedRestored == Other.CalleeSavedRestored;
+           CalleeSavedRestored == Other.CalleeSavedRestored &&
+           DebugVar == Other.DebugVar && DebugExpr == Other.DebugExpr
+           && DebugLoc == Other.DebugLoc;
   }
 };
 
@@ -321,6 +326,12 @@ template <> struct MappingTraits<FixedMa
                        StringValue()); // Don't print it out when it's empty.
     YamlIO.mapOptional("callee-saved-restored", Object.CalleeSavedRestored,
                      true);
+    YamlIO.mapOptional("debug-info-variable", Object.DebugVar,
+                       StringValue()); // Don't print it out when it's empty.
+    YamlIO.mapOptional("debug-info-expression", Object.DebugExpr,
+                       StringValue()); // Don't print it out when it's empty.
+    YamlIO.mapOptional("debug-info-location", Object.DebugLoc,
+                       StringValue()); // Don't print it out when it's empty.
   }
 
   static const bool flow = true;

Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunction.h?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineFunction.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineFunction.h Wed Apr 25 11:58:06 2018
@@ -349,11 +349,12 @@ public:
   struct VariableDbgInfo {
     const DILocalVariable *Var;
     const DIExpression *Expr;
-    unsigned Slot;
+    // The Slot can be negative for fixed stack objects.
+    int Slot;
     const DILocation *Loc;
 
     VariableDbgInfo(const DILocalVariable *Var, const DIExpression *Expr,
-                    unsigned Slot, const DILocation *Loc)
+                    int Slot, const DILocation *Loc)
         : Var(Var), Expr(Expr), Slot(Slot), Loc(Loc) {}
   };
   using VariableDbgInfoMapTy = SmallVector<VariableDbgInfo, 4>;
@@ -860,7 +861,7 @@ public:
 
   /// Collect information used to emit debugging information of a variable.
   void setVariableDbgInfo(const DILocalVariable *Var, const DIExpression *Expr,
-                          unsigned Slot, const DILocation *Loc) {
+                          int Slot, const DILocation *Loc) {
     VariableDbgInfos.emplace_back(Var, Expr, Slot, Loc);
   }
 

Modified: llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp Wed Apr 25 11:58:06 2018
@@ -122,8 +122,9 @@ public:
                                 const yaml::StringValue &RegisterSource,
                                 bool IsRestored, int FrameIdx);
 
+  template <typename T>
   bool parseStackObjectsDebugInfo(PerFunctionMIParsingState &PFS,
-                                  const yaml::MachineStackObject &Object,
+                                  const T &Object,
                                   int FrameIdx);
 
   bool initializeConstantPool(PerFunctionMIParsingState &PFS,
@@ -616,6 +617,8 @@ bool MIRParserImpl::initializeFrameInfo(
     if (parseCalleeSavedRegister(PFS, CSIInfo, Object.CalleeSavedRegister,
                                  Object.CalleeSavedRestored, ObjectIdx))
       return true;
+    if (parseStackObjectsDebugInfo(PFS, Object, ObjectIdx))
+      return true;
   }
 
   // Initialize the ordinary frame objects.
@@ -700,11 +703,11 @@ static bool typecheckMDNode(T *&Result,
   return false;
 }
 
+template <typename T>
 bool MIRParserImpl::parseStackObjectsDebugInfo(PerFunctionMIParsingState &PFS,
-    const yaml::MachineStackObject &Object, int FrameIdx) {
+    const T &Object, int FrameIdx) {
   // Debug information can only be attached to stack objects; Fixed stack
   // objects aren't supported.
-  assert(FrameIdx >= 0 && "Expected a stack object frame index");
   MDNode *Var = nullptr, *Expr = nullptr, *Loc = nullptr;
   if (parseMDNode(PFS, Var, Object.DebugVar) ||
       parseMDNode(PFS, Expr, Object.DebugExpr) ||
@@ -719,7 +722,7 @@ bool MIRParserImpl::parseStackObjectsDeb
       typecheckMDNode(DIExpr, Expr, Object.DebugExpr, "DIExpression", *this) ||
       typecheckMDNode(DILoc, Loc, Object.DebugLoc, "DILocation", *this))
     return true;
-  PFS.MF.setVariableDbgInfo(DIVar, DIExpr, unsigned(FrameIdx), DILoc);
+  PFS.MF.setVariableDbgInfo(DIVar, DIExpr, FrameIdx, DILoc);
   return false;
 }
 

Modified: llvm/trunk/lib/CodeGen/MIRPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRPrinter.cpp Wed Apr 25 11:58:06 2018
@@ -256,6 +256,21 @@ static void printRegClassOrBank(unsigned
   OS << printRegClassOrBank(Reg, RegInfo, TRI);
 }
 
+template <typename T>
+static void
+printStackObjectDbgInfo(const MachineFunction::VariableDbgInfo &DebugVar,
+                        T &Object, ModuleSlotTracker &MST) {
+  std::array<std::string *, 3> Outputs{{&Object.DebugVar.Value,
+                                        &Object.DebugExpr.Value,
+                                        &Object.DebugLoc.Value}};
+  std::array<const Metadata *, 3> Metas{{DebugVar.Var,
+                                        DebugVar.Expr,
+                                        DebugVar.Loc}};
+  for (unsigned i = 0; i < 3; ++i) {
+    raw_string_ostream StrOS(*Outputs[i]);
+    Metas[i]->printAsOperand(StrOS, MST);
+  }
+}
 
 void MIRPrinter::convert(yaml::MachineFunction &MF,
                          const MachineRegisterInfo &RegInfo,
@@ -421,19 +436,12 @@ void MIRPrinter::convertStackObjects(yam
     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
            "Invalid stack object index");
     const FrameIndexOperand &StackObject = StackObjectInfo->second;
-    assert(!StackObject.IsFixed && "Expected a non-fixed stack object");
-    auto &Object = YMF.StackObjects[StackObject.ID];
-    {
-      raw_string_ostream StrOS(Object.DebugVar.Value);
-      DebugVar.Var->printAsOperand(StrOS, MST);
-    }
-    {
-      raw_string_ostream StrOS(Object.DebugExpr.Value);
-      DebugVar.Expr->printAsOperand(StrOS, MST);
-    }
-    {
-      raw_string_ostream StrOS(Object.DebugLoc.Value);
-      DebugVar.Loc->printAsOperand(StrOS, MST);
+    if (StackObject.IsFixed) {
+      auto &Object = YMF.FixedStackObjects[StackObject.ID];
+      printStackObjectDbgInfo(DebugVar, Object, MST);
+    } else {
+      auto &Object = YMF.StackObjects[StackObject.ID];
+      printStackObjectDbgInfo(DebugVar, Object, MST);
     }
   }
 }

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll Wed Apr 25 11:58:06 2018
@@ -33,13 +33,13 @@ define i64 @muli64(i64 %arg1, i64 %arg2)
 ; CHECK: stack:
 ; CHECK-NEXT:   - { id: 0, name: ptr1, type: default, offset: 0, size: 8, alignment: 8,
 ; CHECK-NEXT:       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-; CHECK-NEXT: di-variable: '', di-expression: '', di-location: '' }
+; CHECK-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 ; CHECK-NEXT:   - { id: 1, name: ptr2, type: default, offset: 0, size: 8, alignment: 1,
 ; CHECK-NEXT:       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-; CHECK-NEXT:       di-variable: '', di-expression: '', di-location: '' }
+; CHECK-NEXT:       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 ; CHECK-NEXT:   - { id: 2, name: ptr3, type: default, offset: 0, size: 128, alignment: 8,
 ; CHECK-NEXT:       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-; CHECK-NEXT:       di-variable: '', di-expression: '', di-location: '' }
+; CHECK-NEXT:       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 ; CHECK-NEXT:   - { id: 3, name: ptr4, type: default, offset: 0, size: 1, alignment: 8,
 ; CHECK: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %stack.0.ptr1
 ; CHECK: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %stack.1.ptr2

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/debug-insts.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/debug-insts.ll?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/debug-insts.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/debug-insts.ll Wed Apr 25 11:58:06 2018
@@ -5,7 +5,7 @@
 ; CHECK: stack:
 ; CHECK:    - { id: {{.*}}, name: in.addr, type: default, offset: 0, size: {{.*}}, alignment: {{.*}},
 ; CHECK-NEXT: callee-saved-register: '', callee-saved-restored: true,
-; CHECK-NEXT: di-variable: '!11', di-expression: '!DIExpression()',
+; CHECK-NEXT: debug-info-variable: '!11', debug-info-expression: '!DIExpression()',
 ; CHECK: DBG_VALUE debug-use %0(s32), debug-use $noreg, !11, !DIExpression(), debug-location !12
 define void @debug_declare(i32 %in) #0 !dbg !7 {
 entry:

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/fp128-legalize-crash-pr35690.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/fp128-legalize-crash-pr35690.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/fp128-legalize-crash-pr35690.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/fp128-legalize-crash-pr35690.mir Wed Apr 25 11:58:06 2018
@@ -25,7 +25,8 @@ fixedStack:
 stack:           
   - { id: 0, name: a.addr, type: default, offset: 0, size: 16, alignment: 16, 
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true, 
-      di-variable: '', di-expression: '', di-location: '' }
+      debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
 body:             |
   bb.1.entry:
     liveins: $q0

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-large.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-large.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-large.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-large.mir Wed Apr 25 11:58:06 2018
@@ -24,7 +24,8 @@ regBankSelected: true
 stack:
   - { id: 0, name: retval, type: default, offset: 0, size: 4, alignment: 4,
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-      di-variable: '', di-expression: '', di-location: '' }
+      debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
 constants:
 body:             |
   bb.1:

Modified: llvm/trunk/test/CodeGen/AArch64/reverse-csr-restore-seq.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/reverse-csr-restore-seq.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/reverse-csr-restore-seq.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/reverse-csr-restore-seq.mir Wed Apr 25 11:58:06 2018
@@ -46,7 +46,8 @@ tracksRegLiveness: true
 stack:
   - { id : 0, size: 8, alignment: 4,
   stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-  local-offset: -4, di-variable: '', di-expression: '', di-location: '' }
+  local-offset: -4, debug-info-variable: '', debug-info-expression: '',
+  debug-info-location: '' }
 
 body:             |
   bb.0:

Modified: llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir Wed Apr 25 11:58:06 2018
@@ -103,11 +103,13 @@ fixedStack:
       isImmutable: false, isAliased: false, callee-saved-register: '' }
 stack:
   - { id: 0, name: scratch0, type: default, offset: 4, size: 32768, alignment: 4,
-      stack-id: 0, callee-saved-register: '', local-offset: 0, di-variable: '',
-      di-expression: '', di-location: '' }
+      stack-id: 0, callee-saved-register: '', local-offset: 0,
+      debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
   - { id: 1, name: scratch1, type: default, offset: 32772, size: 32768,
       alignment: 4, stack-id: 0, callee-saved-register: '', local-offset: 32768,
-      di-variable: '', di-expression: '', di-location: '' }
+      debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
 constants:
 body:             |
   bb.0.entry:

Modified: llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir Wed Apr 25 11:58:06 2018
@@ -101,11 +101,13 @@ fixedStack:
       isImmutable: false, isAliased: false, callee-saved-register: '' }
 stack:
   - { id: 0, name: scratch0, type: default, offset: 4, size: 32768, alignment: 4,
-      stack-id: 0, callee-saved-register: '', local-offset: 0, di-variable: '',
-      di-expression: '', di-location: '' }
+      stack-id: 0, callee-saved-register: '', local-offset: 0,
+      debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
   - { id: 1, name: scratch1, type: default, offset: 32772, size: 32768,
       alignment: 4, stack-id: 0, callee-saved-register: '', local-offset: 32768,
-      di-variable: '', di-expression: '', di-location: '' }
+      debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
 constants:
 body:             |
   bb.0.entry:

Modified: llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir Wed Apr 25 11:58:06 2018
@@ -101,11 +101,13 @@ fixedStack:
       isImmutable: false, isAliased: false, callee-saved-register: '' }
 stack:
   - { id: 0, name: scratch0, type: default, offset: 4, size: 32768, alignment: 4,
-      stack-id: 0, callee-saved-register: '', local-offset: 0, di-variable: '',
-      di-expression: '', di-location: '' }
+      stack-id: 0, callee-saved-register: '', local-offset: 0,
+      debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
   - { id: 1, name: scratch1, type: default, offset: 32772, size: 32768,
       alignment: 4, stack-id: 0, callee-saved-register: '', local-offset: 32768,
-      di-variable: '', di-expression: '', di-location: '' }
+      debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
 constants:
 body:             |
   bb.0.entry:

Modified: llvm/trunk/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir Wed Apr 25 11:58:06 2018
@@ -188,7 +188,8 @@ fixedStack:
 stack:
   - { id: 0, name: tmp5, type: default, offset: 0, size: 128, alignment: 16,
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-      local-offset: 0, di-variable: '', di-expression: '', di-location: '' }
+      local-offset: 0, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
 constants:
 body:             |
   bb.0.bb:

Modified: llvm/trunk/test/CodeGen/AMDGPU/twoaddr-mad.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/twoaddr-mad.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/twoaddr-mad.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/twoaddr-mad.mir Wed Apr 25 11:58:06 2018
@@ -179,8 +179,8 @@ registers:
   - { id: 2, class: vgpr_32 }
 stack:
   - { id: 0, name: "", type: default, offset: 0, size: 128, alignment: 8,
-      callee-saved-register: '', local-offset: 0, di-variable: '', di-expression: '',
-      di-location: '' }
+      callee-saved-register: '', local-offset: 0, debug-info-variable: '',
+      debug-info-expression: '', debug-info-location: '' }
 body:             |
   bb.0:
 

Modified: llvm/trunk/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir Wed Apr 25 11:58:06 2018
@@ -35,7 +35,8 @@ liveins:
 stack:
   - { id: 0, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4,
       stack-id: 1, callee-saved-register: '', callee-saved-restored: true,
-      di-variable: '', di-expression: '', di-location: '' }
+      debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
 constants:
 body:             |
   bb.0:
@@ -98,7 +99,8 @@ liveins:
 stack:
   - { id: 0, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4,
       stack-id: 1, callee-saved-register: '', callee-saved-restored: true,
-      di-variable: '', di-expression: '', di-location: '' }
+      debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
 constants:
 body:             |
   bb.0:

Modified: llvm/trunk/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir Wed Apr 25 11:58:06 2018
@@ -44,8 +44,8 @@ registers:
   - { id: 2, class: vgpr_32 }
 stack:
   - { id: 0, name: alloca, type: default, offset: 0, size: 128, alignment: 8,
-      callee-saved-register: '', local-offset: 0, di-variable: '', di-expression: '',
-      di-location: '' }
+      callee-saved-register: '', local-offset: 0, debug-info-variable: '',
+      debug-info-expression: '', debug-info-location: '' }
 body:             |
   bb.0:
     %0 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec
@@ -65,8 +65,8 @@ registers:
   - { id: 2, class: vgpr_32 }
 stack:
   - { id: 0, name: alloca, type: default, offset: 0, size: 128, alignment: 8,
-      callee-saved-register: '', local-offset: 0, di-variable: '', di-expression: '',
-      di-location: '' }
+      callee-saved-register: '', local-offset: 0, debug-info-variable: '',
+      debug-info-expression: '', debug-info-location: '' }
 body:             |
   bb.0:
     %0 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec
@@ -87,8 +87,8 @@ registers:
   - { id: 2, class: vgpr_32 }
 stack:
   - { id: 0, name: alloca, type: default, offset: 0, size: 128, alignment: 8,
-      callee-saved-register: '', local-offset: 0, di-variable: '', di-expression: '',
-      di-location: '' }
+      callee-saved-register: '', local-offset: 0, debug-info-variable: '',
+      debug-info-expression: '', debug-info-location: '' }
 body:             |
   bb.0:
     %0 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec
@@ -109,8 +109,8 @@ registers:
   - { id: 2, class: vgpr_32 }
 stack:
   - { id: 0, name: alloca, type: default, offset: 0, size: 128, alignment: 8,
-      callee-saved-register: '', local-offset: 0, di-variable: '', di-expression: '',
-      di-location: '' }
+      callee-saved-register: '', local-offset: 0, debug-info-variable: '',
+      debug-info-expression: '', debug-info-location: '' }
 body:             |
   bb.0:
     %0 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec
@@ -130,8 +130,8 @@ registers:
   - { id: 2, class: vgpr_32 }
 stack:
   - { id: 0, name: alloca, type: default, offset: 0, size: 128, alignment: 8,
-      callee-saved-register: '', local-offset: 0, di-variable: '', di-expression: '',
-      di-location: '' }
+      callee-saved-register: '', local-offset: 0, debug-info-variable: '',
+      debug-info-expression: '', debug-info-location: '' }
 body:             |
   bb.0:
     %0 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec
@@ -151,8 +151,8 @@ registers:
   - { id: 2, class: vgpr_32 }
 stack:
   - { id: 0, name: alloca, type: default, offset: 0, size: 128, alignment: 8,
-      callee-saved-register: '', local-offset: 0, di-variable: '', di-expression: '',
-      di-location: '' }
+      callee-saved-register: '', local-offset: 0, debug-info-variable: '',
+      debug-info-expression: '', debug-info-location: '' }
 body:             |
   bb.0:
     %0 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec

Modified: llvm/trunk/test/CodeGen/ARM/fp16-litpool2-arm.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fp16-litpool2-arm.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fp16-litpool2-arm.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/fp16-litpool2-arm.mir Wed Apr 25 11:58:06 2018
@@ -67,7 +67,8 @@ fixedStack:
 stack:
   - { id: 0, name: res, type: default, offset: -2, size: 2, alignment: 2,
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-      local-offset: -2, di-variable: '', di-expression: '', di-location: '' }
+      local-offset: -2, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
 constants:
   - id:              0
     value:           half 0xH706B

Modified: llvm/trunk/test/CodeGen/ARM/fp16-litpool3-arm.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fp16-litpool3-arm.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fp16-litpool3-arm.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/fp16-litpool3-arm.mir Wed Apr 25 11:58:06 2018
@@ -68,7 +68,8 @@ fixedStack:
 stack:
   - { id: 0, name: res, type: default, offset: -2, size: 2, alignment: 2,
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-      local-offset: -2, di-variable: '', di-expression: '', di-location: '' }
+      local-offset: -2, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
 constants:
   - id:              0
     value:           half 0xH706B

Modified: llvm/trunk/test/CodeGen/MIR/AArch64/mirCanonCopyCopyProp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/mirCanonCopyCopyProp.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AArch64/mirCanonCopyCopyProp.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AArch64/mirCanonCopyCopyProp.mir Wed Apr 25 11:58:06 2018
@@ -6,25 +6,32 @@ name: Proc8
 stack:
   - { id: 0, type: default, offset: 0, size: 4, alignment: 4,
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-      local-offset: -4, di-variable: '', di-expression: '', di-location: '' }
+      local-offset: -4, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
   - { id: 1, type: default, offset: 0, size: 8, alignment: 8,
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-      local-offset: -16, di-variable: '', di-expression: '', di-location: '' }
+      local-offset: -16, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
   - { id: 2, type: default, offset: 0, size: 8, alignment: 8,
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-      local-offset: -24, di-variable: '', di-expression: '', di-location: '' }
+      local-offset: -24, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
   - { id: 3, type: default, offset: 0, size: 8, alignment: 8,
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-      local-offset: -32, di-variable: '', di-expression: '', di-location: '' }
+      local-offset: -32, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
   - { id: 4, type: default, offset: 0, size: 8, alignment: 8,
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-      local-offset: -40, di-variable: '', di-expression: '', di-location: '' }
+      local-offset: -40, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
   - { id: 5, type: default, offset: 0, size: 8, alignment: 8,
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-      local-offset: -48, di-variable: '', di-expression: '', di-location: '' }
+      local-offset: -48, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
   - { id: 6, type: default, offset: 0, size: 8, alignment: 8,
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-      local-offset: -56, di-variable: '', di-expression: '', di-location: '' }
+      local-offset: -56, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
 constants:
 body: |
   bb.0:

Modified: llvm/trunk/test/CodeGen/MIR/AArch64/mirCanonIdempotent.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/mirCanonIdempotent.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AArch64/mirCanonIdempotent.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AArch64/mirCanonIdempotent.mir Wed Apr 25 11:58:06 2018
@@ -11,25 +11,32 @@ name: Proc8
 stack:
   - { id: 0, type: default, offset: 0, size: 4, alignment: 4,
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-      local-offset: -4, di-variable: '', di-expression: '', di-location: '' }
+      local-offset: -4, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
   - { id: 1, type: default, offset: 0, size: 8, alignment: 8,
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-      local-offset: -16, di-variable: '', di-expression: '', di-location: '' }
+      local-offset: -16, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
   - { id: 2, type: default, offset: 0, size: 8, alignment: 8,
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-      local-offset: -24, di-variable: '', di-expression: '', di-location: '' }
+      local-offset: -24, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
   - { id: 3, type: default, offset: 0, size: 8, alignment: 8,
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-      local-offset: -32, di-variable: '', di-expression: '', di-location: '' }
+      local-offset: -32, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
   - { id: 4, type: default, offset: 0, size: 8, alignment: 8,
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-      local-offset: -40, di-variable: '', di-expression: '', di-location: '' }
+      local-offset: -40, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
   - { id: 5, type: default, offset: 0, size: 8, alignment: 8,
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-      local-offset: -48, di-variable: '', di-expression: '', di-location: '' }
+      local-offset: -48, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
   - { id: 6, type: default, offset: 0, size: 8, alignment: 8,
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-      local-offset: -56, di-variable: '', di-expression: '', di-location: '' }
+      local-offset: -56, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
 constants:
 body: |
   bb.0:

Modified: llvm/trunk/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir Wed Apr 25 11:58:06 2018
@@ -27,7 +27,8 @@ frameInfo:
 # CHECK: stack:
 # CHECK: - { id: 0, name: local_var, type: default, offset: 0, size: 8, alignment: 8,
 # CHECK-NEXT: stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-# CHECK-NEXT: local-offset: -8, di-variable: '', di-expression: '', di-location: '' }
+# CHECK-NEXT: local-offset: -8, debug-info-variable: '', debug-info-expression: '',
+# CHECK-NEXT: debug-info-location: '' }
 stack:
   - { id: 0,name: local_var,offset: 0,size: 8,alignment: 8, local-offset: -8 }
 body: |

Modified: llvm/trunk/test/CodeGen/MIR/X86/callee-saved-info.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/callee-saved-info.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/callee-saved-info.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/callee-saved-info.mir Wed Apr 25 11:58:06 2018
@@ -50,7 +50,7 @@ frameInfo:
   adjustsStack:    true
   hasCalls:        true
 # CHECK: fixedStack:
-# CHECK: callee-saved-register: '$rbx', callee-saved-restored: true }
+# CHECK: callee-saved-register: '$rbx', callee-saved-restored: true
 fixedStack:
   - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '$rbx' }
 # CHECK: stack:

Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir Wed Apr 25 11:58:06 2018
@@ -13,8 +13,9 @@ name:            test
 liveins:
   - { reg: '$edi' }
 stack:
-# CHECK: [[@LINE+1]]:74: expected a metadata node
-  - { id: 0, name: xa, offset: -12, size: 4, alignment: 4, di-variable: '0' }
+  - { id: 0, name: xa, offset: -12, size: 4, alignment: 4,
+# CHECK: [[@LINE+1]]:29: expected a metadata node
+      debug-info-variable: '0' }
 body: |
   bb.0.entry:
     liveins: $edi

Added: llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-di.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-di.mir?rev=330859&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-di.mir (added)
+++ llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-di.mir Wed Apr 25 11:58:06 2018
@@ -0,0 +1,42 @@
+# RUN: llc -mtriple=x86_64-apple-unknown -run-pass none %s -o /dev/null
+# Check that we parse the 'debug-info-*' fields for `fixedStack:` entries.
+
+--- |
+
+  target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+  target triple = "x86_64-apple-unknown"
+
+  declare void @llvm.dbg.declare(metadata, metadata, metadata) #0
+
+  define hidden void @foo(i32* byval %dstRect) {
+  entry:
+    call void @llvm.dbg.declare(metadata i32* %dstRect, metadata !3, metadata !DIExpression()), !dbg !5
+    unreachable
+  }
+
+  attributes #0 = { nounwind readnone speculatable }
+
+  !llvm.dbg.cu = !{!0}
+  !llvm.module.flags = !{!2}
+
+  !0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1)
+  !1 = !DIFile(filename: "file.cpp", directory: "/dir")
+  !2 = !{i32 2, !"Debug Info Version", i32 3}
+  !3 = !DILocalVariable(name: "dstRect", scope: !4)
+  !4 = distinct !DISubprogram(name: "foo", linkageName: "foo", scope: !0, file: !1, line: 42, unit: !0)
+  !5 = !DILocation(line: 42, column: 85, scope: !4)
+
+...
+---
+name:            foo
+alignment:       4
+tracksRegLiveness: true
+frameInfo:
+  maxAlignment:    8
+fixedStack:
+  - { id: 0, size: 4, alignment: 16, stack-id: 0, debug-info-variable: '!3', debug-info-expression: '!DIExpression()',
+      debug-info-location: '!5' }
+body:             |
+  bb.0.entry:
+
+...

Modified: llvm/trunk/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir Wed Apr 25 11:58:06 2018
@@ -38,9 +38,10 @@ tracksRegLiveness: true
 frameInfo:
   maxAlignment:    16
 stack:
-# CHECK: [[@LINE+1]]:75: expected a reference to a 'DILocalVariable' metadata node
-  - { id: 0, name: y.i, offset: 0, size: 256, alignment: 16, di-variable: '!8',
-      di-expression: '!7', di-location: '!8' }
+  - { id: 0, name: y.i, offset: 0, size: 256, alignment: 16,
+# CHECK: [[@LINE+1]]:28: expected a reference to a 'DILocalVariable' metadata node
+      debug-info-variable: '!8', debug-info-expression: '!7',
+      debug-info-location: '!8' }
 body: |
   bb.0.entry:
     successors: %bb.1.for.body

Modified: llvm/trunk/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir Wed Apr 25 11:58:06 2018
@@ -20,7 +20,8 @@ frameInfo:
   maxAlignment:    4
 # CHECK: fixedStack:
 # CHECK-NEXT: - { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4, stack-id: 0,
-# CHECK-NEXT: callee-saved-register: '', callee-saved-restored: true }
+# CHECK-NEXT: callee-saved-register: '', callee-saved-restored: true, debug-info-variable: '',
+# CHECK-NEXT: debug-info-expression: '', debug-info-location: '' }
 fixedStack:
   - { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4 }
 stack:

Modified: llvm/trunk/test/CodeGen/MIR/X86/stack-object-debug-info.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/stack-object-debug-info.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/stack-object-debug-info.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/stack-object-debug-info.mir Wed Apr 25 11:58:06 2018
@@ -52,10 +52,12 @@ frameInfo:
 # CHECK: stack:
 # CHECK:  - { id: 0, name: y.i, type: default, offset: 0, size: 256, alignment: 16,
 # CHECK-NEXT: callee-saved-register: '', callee-saved-restored: true,
-# CHECK-NEXT: di-variable: '!4', di-expression: '!DIExpression()', di-location: '!10' }
+# CHECK-NEXT: debug-info-variable: '!4', debug-info-expression: '!DIExpression()',
+# CHECK-NEXT: debug-info-location: '!10' }
 stack:
-  - { id: 0, name: y.i, offset: 0, size: 256, alignment: 16, di-variable: '!4',
-      di-expression: '!DIExpression()', di-location: '!7' }
+  - { id: 0, name: y.i, offset: 0, size: 256, alignment: 16,
+      debug-info-variable: '!4', debug-info-expression: '!DIExpression()',
+      debug-info-location: '!7' }
 body: |
   bb.0.entry:
     successors: %bb.1.for.body

Modified: llvm/trunk/test/CodeGen/MIR/X86/stack-objects.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/stack-objects.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/stack-objects.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/stack-objects.mir Wed Apr 25 11:58:06 2018
@@ -23,13 +23,13 @@ frameInfo:
 # CHECK: stack:
 # CHECK-NEXT: - { id: 0, name: b, type: default, offset: -12, size: 4, alignment: 4,
 # CHECK-NEXT: stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-# CHECK-NEXT: di-variable: '', di-expression: '', di-location: '' }
+# CHECK-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 # CHECK-NEXT: - { id: 1, name: x, type: default, offset: -24, size: 8, alignment: 8,
 # CHECK-NEXT: stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-# CHECK-NEXT: di-variable: '', di-expression: '', di-location: '' }
+# CHECK-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 # CHECK-NEXT: - { id: 2, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4,
 # CHECK-NEXT: stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-# CHECK-NEXT: di-variable: '', di-expression: '', di-location: '' }
+# CHECK-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 stack:
   - { id: 0, name: b, offset: -12, size: 4, alignment: 4 }
   - { id: 1, name: x, offset: -24, size: 8, alignment: 8 }

Modified: llvm/trunk/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir Wed Apr 25 11:58:06 2018
@@ -26,10 +26,10 @@ frameInfo:
 # CHECK: stack:
 # CHECK-NEXT: - { id: 0, name: '', type: default, offset: -20, size: 4, alignment: 4,
 # CHECK-NEXT:  stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-# CHECK-NEXT: di-variable: '', di-expression: '', di-location: '' }
+# CHECK-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 # CHECK-NEXT: - { id: 1, name: '', type: default, offset: -32, size: 8, alignment: 8,
 # CHECK-NEXT:  stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-# CHECK-NEXT: di-variable: '', di-expression: '', di-location: '' }
+# CHECK-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 # CHECK-NEXT: - { id: 2, name: y, type: variable-sized, offset: -32, alignment: 1,
 stack:
   - { id: 0, offset: -20, size: 4, alignment: 4 }

Modified: llvm/trunk/test/CodeGen/Mips/micromips-eva.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/micromips-eva.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/micromips-eva.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/micromips-eva.mir Wed Apr 25 11:58:06 2018
@@ -163,7 +163,8 @@ fixedStack:
 stack:
   - { id: 0, name: z.addr, type: default, offset: 0, size: 4, alignment: 4,
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-      di-variable: '', di-expression: '', di-location: '' }
+      debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
 constants:
 body:             |
   bb.0.entry:

Modified: llvm/trunk/test/CodeGen/Mips/micromips-short-delay-slot.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/micromips-short-delay-slot.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/micromips-short-delay-slot.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/micromips-short-delay-slot.mir Wed Apr 25 11:58:06 2018
@@ -49,7 +49,8 @@ fixedStack:
 stack:
   - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
       stack-id: 0, callee-saved-register: '$ra', callee-saved-restored: true,
-      di-variable: '', di-expression: '', di-location: '' }
+      debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
 constants:
 body:             |
   bb.0.entry:

Modified: llvm/trunk/test/CodeGen/Mips/msa/emergency-spill.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/emergency-spill.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/emergency-spill.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/emergency-spill.mir Wed Apr 25 11:58:06 2018
@@ -102,23 +102,32 @@ frameInfo:
 fixedStack:
 stack:
   - { id: 0, name: retval, type: default, offset: 0, size: 16, alignment: 16,
-      callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+      callee-saved-register: '', debug-info-variable: '',
+      debug-info-expression: '', debug-info-location: '' }
   - { id: 1, name: a, type: default, offset: 0, size: 16, alignment: 16,
-      callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+      callee-saved-register: '', debug-info-variable: '',
+      debug-info-expression: '', debug-info-location: '' }
   - { id: 2, name: b, type: default, offset: 0, size: 16, alignment: 16,
-      callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+      callee-saved-register: '', debug-info-variable: '',
+      debug-info-expression: '', debug-info-location: '' }
   - { id: 3, name: a.addr, type: default, offset: 0, size: 16, alignment: 16,
-      callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+      callee-saved-register: '', debug-info-variable: '',
+      debug-info-expression: '', debug-info-location: '' }
   - { id: 4, name: b.addr, type: default, offset: 0, size: 16, alignment: 16,
-      callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+      callee-saved-register: '', debug-info-variable: '',
+      debug-info-expression: '', debug-info-location: '' }
   - { id: 5, name: c.addr, type: default, offset: 0, size: 4, alignment: 4,
-      callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+      callee-saved-register: '', debug-info-variable: '',
+      debug-info-expression: '', debug-info-location: '' }
   - { id: 6, name: g, type: default, offset: 0, size: 8, alignment: 8,
-      callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+      callee-saved-register: '', debug-info-variable: '',
+      debug-info-expression: '', debug-info-location: '' }
   - { id: 7, name: d, type: default, offset: 0, size: 8, alignment: 8,
-      callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+      callee-saved-register: '', debug-info-variable: '',
+      debug-info-expression: '', debug-info-location: '' }
   - { id: 8, name: '', type: default, offset: 0, size: 6400,
-      alignment: 16, callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+      alignment: 16, callee-saved-register: '', debug-info-variable: '',
+      debug-info-expression: '', debug-info-location: '' }
 constants:
 body:             |
   bb.0.entry:

Modified: llvm/trunk/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir (original)
+++ llvm/trunk/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir Wed Apr 25 11:58:06 2018
@@ -3075,19 +3075,24 @@ fixedStack:
 stack:           
   - { id: 0, name: '', type: default, offset: 0, size: 16, alignment: 16, 
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true, 
-      local-offset: -16, di-variable: '', di-expression: '', di-location: '' }
+      local-offset: -16, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
   - { id: 1, name: '', type: default, offset: 0, size: 4, alignment: 4, 
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true, 
-      local-offset: -20, di-variable: '', di-expression: '', di-location: '' }
+      local-offset: -20, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
   - { id: 2, name: '', type: default, offset: 0, size: 4, alignment: 4, 
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true, 
-      local-offset: -24, di-variable: '', di-expression: '', di-location: '' }
+      local-offset: -24, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
   - { id: 3, name: '', type: default, offset: 0, size: 4, alignment: 4, 
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true, 
-      local-offset: -28, di-variable: '', di-expression: '', di-location: '' }
+      local-offset: -28, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
   - { id: 4, name: '', type: default, offset: 0, size: 4, alignment: 4, 
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true, 
-      local-offset: -32, di-variable: '', di-expression: '', di-location: '' }
+      local-offset: -32, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
 constants:       
 body:             |
   bb.0.entry:

Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/x32-select-frameIndex.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/x32-select-frameIndex.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/x32-select-frameIndex.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/x32-select-frameIndex.mir Wed Apr 25 11:58:06 2018
@@ -19,7 +19,8 @@ fixedStack:
 stack:
   - { id: 0, name: ptr1, type: default, offset: 0, size: 4, alignment: 4,
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-      di-variable: '', di-expression: '', di-location: '' }
+      debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
 
 body:             |
   bb.1 (%ir-block.0):

Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/x86-select-frameIndex.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/x86-select-frameIndex.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/x86-select-frameIndex.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/x86-select-frameIndex.mir Wed Apr 25 11:58:06 2018
@@ -19,7 +19,8 @@ fixedStack:
 stack:
   - { id: 0, name: ptr1, type: default, offset: 0, size: 4, alignment: 4,
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-      di-variable: '', di-expression: '', di-location: '' }
+      debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
 
 body:             |
   bb.1 (%ir-block.0):

Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-select-frameIndex.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-select-frameIndex.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-select-frameIndex.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-select-frameIndex.mir Wed Apr 25 11:58:06 2018
@@ -19,7 +19,8 @@ fixedStack:
 stack:
   - { id: 0, name: ptr1, type: default, offset: 0, size: 4, alignment: 4,
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-      di-variable: '', di-expression: '', di-location: '' }
+      debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
 
 body:             |
   bb.1 (%ir-block.0):

Added: llvm/trunk/test/CodeGen/X86/fixed-stack-di-mir.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fixed-stack-di-mir.ll?rev=330859&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fixed-stack-di-mir.ll (added)
+++ llvm/trunk/test/CodeGen/X86/fixed-stack-di-mir.ll Wed Apr 25 11:58:06 2018
@@ -0,0 +1,32 @@
+; RUN: llc -mtriple=x86_64-apple-unknown -stop-before=expand-isel-pseudos %s -o - -simplify-mir | FileCheck %s
+; The byval argument of the function will be allocated a fixed stack slot. Test
+; that we serialize the fixed slot correctly.
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-unknown"
+
+declare void @llvm.dbg.declare(metadata, metadata, metadata) #0
+
+define hidden void @foo(i32* byval %dstRect) {
+; CHECK-LABEL: name: foo
+entry:
+  call void @llvm.dbg.declare(metadata i32* %dstRect, metadata !3, metadata !DIExpression()), !dbg !5
+; CHECK: fixedStack:
+; CHECK: id: 0
+; CHECK: debug-info-variable: '!3'
+; CHECK: debug-info-expression: '!DIExpression()'
+; CHECK: debug-info-location: '!5'
+  unreachable
+}
+
+attributes #0 = { nounwind readnone speculatable }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!2}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1)
+!1 = !DIFile(filename: "file.cpp", directory: "/dir")
+!2 = !{i32 2, !"Debug Info Version", i32 3}
+!3 = !DILocalVariable(name: "dstRect", scope: !4)
+!4 = distinct !DISubprogram(name: "foo", linkageName: "foo", scope: !0, file: !1, line: 42, unit: !0)
+!5 = !DILocation(line: 42, column: 85, scope: !4)

Modified: llvm/trunk/test/CodeGen/X86/movtopush.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/movtopush.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/movtopush.mir (original)
+++ llvm/trunk/test/CodeGen/X86/movtopush.mir Wed Apr 25 11:58:06 2018
@@ -89,13 +89,16 @@ fixedStack:
 stack:
   - { id: 0, name: p, type: default, offset: 0, size: 4, alignment: 4,
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-      di-variable: '', di-expression: '', di-location: '' }
+      debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
   - { id: 1, name: q, type: default, offset: 0, size: 4, alignment: 4,
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-      di-variable: '', di-expression: '', di-location: '' }
+      debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
   - { id: 2, name: s, type: default, offset: 0, size: 8, alignment: 8,
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-      di-variable: '', di-expression: '', di-location: '' }
+      debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
 constants:
 body:             |
   bb.0.entry:

Modified: llvm/trunk/test/CodeGen/X86/pr30821.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr30821.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr30821.mir (original)
+++ llvm/trunk/test/CodeGen/X86/pr30821.mir Wed Apr 25 11:58:06 2018
@@ -47,13 +47,14 @@ fixedStack:
 stack:
   - { id: 0, name: alpha, type: default, offset: 0, size: 1, alignment: 1,
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-      di-variable: '', di-expression: '', di-location: '' }
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
   - { id: 1, name: foxtrot, type: default, offset: 0, size: 16, alignment: 16,
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-      di-variable: '', di-expression: '', di-location: '' }
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
   - { id: 2, name: india, type: default, offset: 0, size: 16, alignment: 16,
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-      di-variable: '', di-expression: '', di-location: '' }
+      debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
 constants:
 body:             |
   bb.0.entry:

Modified: llvm/trunk/test/DebugInfo/MIR/AArch64/implicit-def-dead-scope.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/MIR/AArch64/implicit-def-dead-scope.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/MIR/AArch64/implicit-def-dead-scope.mir (original)
+++ llvm/trunk/test/DebugInfo/MIR/AArch64/implicit-def-dead-scope.mir Wed Apr 25 11:58:06 2018
@@ -173,14 +173,14 @@ frameInfo:
 fixedStack:      
 stack:           
   - { id: 0, name: bz, type: default, offset: -32, size: 16, alignment: 8, 
-      callee-saved-register: '', local-offset: -16, di-variable: '', di-expression: '', 
-      di-location: '' }
+      callee-saved-register: '', local-offset: -16, debug-info-variable: '',
+      debug-info-expression: '', debug-info-location: '' }
   - { id: 1, name: att, type: default, offset: -48, size: 16, alignment: 8, 
-      callee-saved-register: '', local-offset: -32, di-variable: '', di-expression: '', 
-      di-location: '' }
+      callee-saved-register: '', local-offset: -32, debug-info-variable: '',
+      debug-info-expression: '', debug-info-location: '' }
   - { id: 2, name: '', type: spill-slot, offset: -16, size: 8, alignment: 16, 
-      callee-saved-register: '$lr', di-variable: '', di-expression: '', 
-      di-location: '' }
+      callee-saved-register: '$lr', debug-info-variable: '',
+      debug-info-expression: '', debug-info-location: '' }
 constants:       
 body:             |
   bb.0.entry:

Modified: llvm/trunk/test/DebugInfo/MIR/Mips/last-inst-bundled.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/MIR/Mips/last-inst-bundled.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/MIR/Mips/last-inst-bundled.mir (original)
+++ llvm/trunk/test/DebugInfo/MIR/Mips/last-inst-bundled.mir Wed Apr 25 11:58:06 2018
@@ -140,13 +140,16 @@ fixedStack:
 stack:
   - { id: 0, name: condition, type: default, offset: -12, size: 4, alignment: 4,
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-      di-variable: '', di-expression: '', di-location: '' }
+      debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
   - { id: 1, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
       stack-id: 0, callee-saved-register: '$ra', callee-saved-restored: true,
-      di-variable: '', di-expression: '', di-location: '' }
+      debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
   - { id: 2, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
       stack-id: 0, callee-saved-register: '$s0', callee-saved-restored: true,
-      di-variable: '', di-expression: '', di-location: '' }
+      debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
 constants:
 body:             |
   bb.0.entry:

Modified: llvm/trunk/test/DebugInfo/MIR/X86/kill-after-spill.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/MIR/X86/kill-after-spill.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/MIR/X86/kill-after-spill.mir (original)
+++ llvm/trunk/test/DebugInfo/MIR/X86/kill-after-spill.mir Wed Apr 25 11:58:06 2018
@@ -246,10 +246,12 @@ fixedStack:
 stack:
   - { id: 0, name: '', type: spill-slot, offset: -64, size: 4, alignment: 4,
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-      di-variable: '', di-expression: '', di-location: '' }
+      debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
   - { id: 1, name: '', type: spill-slot, offset: -60, size: 4, alignment: 4,
       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
-      di-variable: '', di-expression: '', di-location: '' }
+      debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
 constants:
 body:             |
   bb.0.entry:

Modified: llvm/trunk/test/DebugInfo/X86/live-debug-vars-dse.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/live-debug-vars-dse.mir?rev=330859&r1=330858&r2=330859&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/X86/live-debug-vars-dse.mir (original)
+++ llvm/trunk/test/DebugInfo/X86/live-debug-vars-dse.mir Wed Apr 25 11:58:06 2018
@@ -119,8 +119,8 @@ frameInfo:
 fixedStack:      
 stack:           
   - { id: 0, name: x.addr, type: default, offset: 0, size: 4, alignment: 4, 
-      stack-id: 0, callee-saved-register: '', di-variable: '', di-expression: '', 
-      di-location: '' }
+      stack-id: 0, callee-saved-register: '', debug-info-variable: '',
+      debug-info-expression: '', debug-info-location: '' }
 constants:       
 body:             |
   bb.0.entry:




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