[PATCH] D46067: [AMDGPU][Waitcnt] Take ISA target into account for s_waitcnt expcnt instr generation

[Mark Searles via Phabricator via llvm-commits]

msearles created this revision.
msearles added a reviewer: t-tye.
msearles added a project: AMDGPU.
Herald added subscribers: tpr, dstuttard, yaxunl, nhaehnle, wdng, kzhuravl, arsenm.

As of gfx7, VMEM operations do not increment the export counter and the input registers are available in the next instruction; update the waitcnt pass to take this into account.


https://reviews.llvm.org/D46067

Files:
  lib/Target/AMDGPU/AMDGPUSubtarget.h
  lib/Target/AMDGPU/SIInsertWaitcnts.cpp
  test/CodeGen/AMDGPU/insert_vector_elt.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.image.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.ll

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