[PATCH] D46018: [GlobalISel][IRTranslator] Split aggregates during IR translation

[Amara Emerson via Phabricator via llvm-commits]

aemerson created this revision.
aemerson added reviewers: dsanders, aditya_nandakumar, qcolombet, bogner, volkan, rtereshin, t.p.northover.
Herald added subscribers: kristof.beyls, rovka.
Herald added a reviewer: javed.absar.

We currently handle all aggregates by creating one large LLT, and letting the legalizer deal with splitting them up. However using this approach means that we can't support big endian code correctly.

This patch changes the way that the IRTranslator deals with aggregate values, by splitting them up into their consistuent element values. To do this, parts of the translator need to be modified to deal with multiple VRegs for a single Value.

A new Value to VReg mapper is introduced to help keep compile time under control, currently there is no measurable impact on CTMark despite the extra code being generated in some cases.

Patch is based on the original work of Tim Northover.


Repository:
  rL LLVM

https://reviews.llvm.org/D46018

Files:
  include/llvm/CodeGen/GlobalISel/IRTranslator.h
  lib/CodeGen/GlobalISel/IRTranslator.cpp
  lib/Target/AArch64/AArch64CallLowering.cpp
  lib/Target/ARM/ARMCallLowering.cpp
  test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
  test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
  test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
  test/CodeGen/AArch64/GlobalISel/call-translator.ll
  test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
  test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
  test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
  test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll

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