[llvm] r330705 - [mips] Correct the patterns for bswap
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 24 03:19:29 PDT 2018
Author: sdardis
Date: Tue Apr 24 03:19:29 2018
New Revision: 330705
URL: http://llvm.org/viewvc/llvm-project?rev=330705&view=rev
Log:
[mips] Correct the patterns for bswap
Guard the MIPS64 variant correctly for i64, mark the MIPS32 version as not
in microMIPS and provide the microMIPS version.
Additionally, remove a related stale XFAIL'd test as bswap has its own test
case providing coverage.
Reviewers: smaksimovic, abeserminji, atanasyan
Differential Revision: https://reviews.llvm.org/D45816
Removed:
llvm/trunk/test/CodeGen/Mips/2008-08-08-bswap.ll
Modified:
llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/CodeGen/Mips/bswap.ll
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=330705&r1=330704&r2=330705&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Tue Apr 24 03:19:29 2018
@@ -1124,6 +1124,9 @@ let Predicates = [InMicroMips] in {
(SUBu_MM GPR32:$lhs, GPR32:$rhs)>;
}
+def : MipsPat<(bswap GPR32:$rt), (ROTR_MM (WSBH_MM GPR32:$rt), 16)>,
+ ISA_MICROMIPS;
+
def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
(TAILCALL_MM tglobaladdr:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;
def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=330705&r1=330704&r2=330705&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Tue Apr 24 03:19:29 2018
@@ -728,7 +728,7 @@ def : MipsPat<(i64 (sext_inreg GPR64:$sr
(SLL64_64 GPR64:$src)>;
// bswap MipsPattern
-def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
+def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>, ISA_MIPS64R2;
// Carry pattern
let AdditionalPredicates = [NotInMicroMips] in {
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=330705&r1=330704&r2=330705&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Apr 24 03:19:29 2018
@@ -3030,10 +3030,10 @@ let AdditionalPredicates = [NotInMicroMi
defm : SetgtPats<GPR32, SLT, SLTu>;
defm : SetgePats<GPR32, XORi, SLT, SLTu>;
defm : SetgeImmPats<GPR32, XORi, SLTi, SLTiu>;
-}
-// bswap pattern
-def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
+ // bswap pattern
+ def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>, ISA_MIPS32R2;
+}
// Load halfword/word patterns.
let AddedComplexity = 40 in {
Removed: llvm/trunk/test/CodeGen/Mips/2008-08-08-bswap.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-08-08-bswap.ll?rev=330704&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/2008-08-08-bswap.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/2008-08-08-bswap.ll (removed)
@@ -1,15 +0,0 @@
-; DISABLED: llc < %s | grep wsbw | count 1
-; RUN: false
-; XFAIL: *
-
-
-target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
-target triple = "psp"
-
-define i32 @__bswapsi2(i32 %u) nounwind {
-entry:
- tail call i32 @llvm.bswap.i32( i32 %u ) ; <i32>:0 [#uses=1]
- ret i32 %0
-}
-
-declare i32 @llvm.bswap.i32(i32) nounwind readnone
Modified: llvm/trunk/test/CodeGen/Mips/bswap.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/bswap.ll?rev=330705&r1=330704&r2=330705&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/bswap.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/bswap.ll Tue Apr 24 03:19:29 2018
@@ -1,4 +1,5 @@
; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=MIPS32
+; RUN: llc < %s -mtriple=mipsel-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips | FileCheck %s -check-prefix=MM
; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=MIPS64
; RUN: llc < %s -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32r2 -mattr=+mips16 | FileCheck %s -check-prefix=MIPS16
@@ -8,6 +9,10 @@ entry:
; MIPS32: wsbh $[[R0:[0-9]+]]
; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
+; MM-LABEL: bswap32:
+; MM: wsbh $[[R0:[0-9]+]]
+; MM: rotr ${{[0-9]+}}, $[[R0]], 16
+
; MIPS64-LABEL: bswap32:
; MIPS64: wsbh $[[R0:[0-9]+]]
; MIPS64: rotr ${{[0-9]+}}, $[[R0]], 16
@@ -37,6 +42,12 @@ entry:
; MIPS32: wsbh $[[R0:[0-9]+]]
; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
+; MM-LABEL: bswap64:
+; MM: wsbh $[[R0:[0-9]+]]
+; MM: rotr ${{[0-9]+}}, $[[R0]], 16
+; MM: wsbh $[[R0:[0-9]+]]
+; MM: rotr ${{[0-9]+}}, $[[R0]], 16
+
; MIPS64-LABEL: bswap64:
; MIPS64: dsbh $[[R0:[0-9]+]]
; MIPS64: dshd ${{[0-9]+}}, $[[R0]]
@@ -81,6 +92,16 @@ entry:
; MIPS32-DAG: wsbh $[[R0:[0-9]+]]
; MIPS32-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
+; MM-LABEL: bswapv4i32:
+; MM-DAG: wsbh $[[R0:[0-9]+]]
+; MM-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
+; MM-DAG: wsbh $[[R0:[0-9]+]]
+; MM-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
+; MM-DAG: wsbh $[[R0:[0-9]+]]
+; MM-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
+; MM-DAG: wsbh $[[R0:[0-9]+]]
+; MM-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
+
; MIPS64-LABEL: bswapv4i32:
; MIPS64-DAG: wsbh $[[R0:[0-9]+]]
; MIPS64-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
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