[llvm] r330648 - [X86] Remove unnecessary WriteLEA InstRW overrides.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 23 14:57:09 PDT 2018
Yes, we need to provide schedule classes to discriminate between the
major LEA modes, possibly covering the various X86 slow lea feature
flags as well as Intel/AMD pipe restrictions - I haven't looked at how
best to do this though. Last year I created PR32326 for a similar reason
but didn't look into it very much.
We might need scheduler predicates to handle these which Andrea is still
investigating at the moment as they're proving tricky to integrate into
llvm-mca.
On 23/04/2018 22:13, Craig Topper wrote:
> What do we want to do about LEAs having different scheduling data
> based on the number of components used in the address?
>
> ~Craig
>
> On Mon, Apr 23, 2018 at 2:04 PM, Simon Pilgrim via llvm-commits
> <llvm-commits at lists.llvm.org <mailto:llvm-commits at lists.llvm.org>> wrote:
>
> Author: rksimon
> Date: Mon Apr 23 14:04:23 2018
> New Revision: 330648
>
> URL: http://llvm.org/viewvc/llvm-project?rev=330648&view=rev
> <http://llvm.org/viewvc/llvm-project?rev=330648&view=rev>
> Log:
> [X86] Remove unnecessary WriteLEA InstRW overrides.
>
>
> Modified:
> llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
> llvm/trunk/lib/Target/X86/X86SchedHaswell.td
> llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
> llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
> llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
>
> Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=330648&r1=330647&r2=330648&view=diff
> <http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=330648&r1=330647&r2=330648&view=diff>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
> +++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Mon Apr 23
> 14:04:23 2018
> @@ -401,8 +401,7 @@ def BWWriteResGroup7 : SchedWriteRes<[BW
> def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr",
> "BLSI(32|64)rr",
> "BLSMSK(32|64)rr",
> - "BLSR(32|64)rr",
> - "LEA(16|32|64)(_32)?r")>;
> + "BLSR(32|64)rr")>;
>
> def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> {
> let Latency = 1;
>
> Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=330648&r1=330647&r2=330648&view=diff
> <http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=330648&r1=330647&r2=330648&view=diff>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
> +++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Mon Apr 23
> 14:04:23 2018
> @@ -745,8 +745,7 @@ def HWWriteResGroup8 : SchedWriteRes<[HW
> def: InstRW<[HWWriteResGroup8], (instregex "ANDN(32|64)rr",
> "BLSI(32|64)rr",
> "BLSMSK(32|64)rr",
> - "BLSR(32|64)rr",
> - "LEA(16|32|64)(_32)?r")>;
> + "BLSR(32|64)rr")>;
>
> def HWWriteResGroup9 : SchedWriteRes<[HWPort015]> {
> let Latency = 1;
>
> Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=330648&r1=330647&r2=330648&view=diff
> <http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=330648&r1=330647&r2=330648&view=diff>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
> +++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Mon Apr 23
> 14:04:23 2018
> @@ -120,7 +120,7 @@ def : WriteRes<WriteSETCCStore, [SBPort
> // This is for simple LEAs with one or two input operands.
> // The complex ones can only execute on port 1, and they require
> two cycles on
> // the port to read all inputs. We don't model that.
> -def : WriteRes<WriteLEA, [SBPort15]>;
> +def : WriteRes<WriteLEA, [SBPort01]>;
>
> // Bit counts.
> defm : SBWriteResPair<WriteBitScan, [SBPort1], 3, [1], 1, 5>;
> @@ -341,13 +341,6 @@ def: InstRW<[SBWriteResGroup2], (instreg
> "(V?)MOV64toPQIrr",
> "(V?)MOVDI2PDIrr")>;
>
> -def SBWriteResGroup3 : SchedWriteRes<[SBPort01]> {
> - let Latency = 1;
> - let NumMicroOps = 1;
> - let ResourceCycles = [1];
> -}
> -def: InstRW<[SBWriteResGroup3], (instregex "LEA(16|32|64)(_32)?r")>;
> -
> def SBWriteResGroup4 : SchedWriteRes<[SBPort05]> {
> let Latency = 1;
> let NumMicroOps = 1;
>
> Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=330648&r1=330647&r2=330648&view=diff
> <http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=330648&r1=330647&r2=330648&view=diff>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
> +++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Mon Apr 23
> 14:04:23 2018
> @@ -485,8 +485,7 @@ def SKLWriteResGroup8 : SchedWriteRes<[S
> def: InstRW<[SKLWriteResGroup8], (instregex "ANDN(32|64)rr",
> "BLSI(32|64)rr",
> "BLSMSK(32|64)rr",
> - "BLSR(32|64)rr",
> - "LEA(16|32|64)(_32)?r")>;
> + "BLSR(32|64)rr")>;
>
> def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> {
> let Latency = 1;
>
> Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=330648&r1=330647&r2=330648&view=diff
> <http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=330648&r1=330647&r2=330648&view=diff>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
> +++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Mon Apr 23
> 14:04:23 2018
> @@ -790,8 +790,7 @@ def SKXWriteResGroup8 : SchedWriteRes<[S
> def: InstRW<[SKXWriteResGroup8], (instregex "ANDN(32|64)rr",
> "BLSI(32|64)rr",
> "BLSMSK(32|64)rr",
> - "BLSR(32|64)rr",
> - "LEA(16|32|64)(_32)?r")>;
> + "BLSR(32|64)rr")>;
>
> def SKXWriteResGroup9 : SchedWriteRes<[SKXPort015]> {
> let Latency = 1;
>
>
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