[llvm] r330583 - [AArch64][SVE] Asm: Support for contiguous, non-faulting LDNF1 (scalar+imm) load instructions
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 23 05:43:19 PDT 2018
Author: s.desmalen
Date: Mon Apr 23 05:43:19 2018
New Revision: 330583
URL: http://llvm.org/viewvc/llvm-project?rev=330583&view=rev
Log:
[AArch64][SVE] Asm: Support for contiguous, non-faulting LDNF1 (scalar+imm) load instructions
Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro
Reviewed By: rengolin
Subscribers: tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45684
Added:
llvm/trunk/test/MC/AArch64/SVE/ldnf1b-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ldnf1b.s
llvm/trunk/test/MC/AArch64/SVE/ldnf1d-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ldnf1d.s
llvm/trunk/test/MC/AArch64/SVE/ldnf1h-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ldnf1h.s
llvm/trunk/test/MC/AArch64/SVE/ldnf1sb-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ldnf1sb.s
llvm/trunk/test/MC/AArch64/SVE/ldnf1sh-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ldnf1sh.s
llvm/trunk/test/MC/AArch64/SVE/ldnf1sw-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ldnf1sw.s
llvm/trunk/test/MC/AArch64/SVE/ldnf1w-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ldnf1w.s
Modified:
llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
Modified: llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td?rev=330583&r1=330582&r2=330583&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td Mon Apr 23 05:43:19 2018
@@ -56,6 +56,24 @@ let Predicates = [HasSVE] in {
defm LD1SB_H : sve_mem_cld_ss<0b1110, "ld1sb", Z_h, ZPR16, GPR64NoXZRshifted8>;
defm LD1D : sve_mem_cld_ss<0b1111, "ld1d", Z_d, ZPR64, GPR64NoXZRshifted64>;
+ // non-faulting continuous load with reg+immediate
+ defm LDNF1B_IMM : sve_mem_cldnf_si<0b0000, "ldnf1b", Z_b, ZPR8>;
+ defm LDNF1B_H_IMM : sve_mem_cldnf_si<0b0001, "ldnf1b", Z_h, ZPR16>;
+ defm LDNF1B_S_IMM : sve_mem_cldnf_si<0b0010, "ldnf1b", Z_s, ZPR32>;
+ defm LDNF1B_D_IMM : sve_mem_cldnf_si<0b0011, "ldnf1b", Z_d, ZPR64>;
+ defm LDNF1SW_D_IMM : sve_mem_cldnf_si<0b0100, "ldnf1sw", Z_d, ZPR64>;
+ defm LDNF1H_IMM : sve_mem_cldnf_si<0b0101, "ldnf1h", Z_h, ZPR16>;
+ defm LDNF1H_S_IMM : sve_mem_cldnf_si<0b0110, "ldnf1h", Z_s, ZPR32>;
+ defm LDNF1H_D_IMM : sve_mem_cldnf_si<0b0111, "ldnf1h", Z_d, ZPR64>;
+ defm LDNF1SH_D_IMM : sve_mem_cldnf_si<0b1000, "ldnf1sh", Z_d, ZPR64>;
+ defm LDNF1SH_S_IMM : sve_mem_cldnf_si<0b1001, "ldnf1sh", Z_s, ZPR32>;
+ defm LDNF1W_IMM : sve_mem_cldnf_si<0b1010, "ldnf1w", Z_s, ZPR32>;
+ defm LDNF1W_D_IMM : sve_mem_cldnf_si<0b1011, "ldnf1w", Z_d, ZPR64>;
+ defm LDNF1SB_D_IMM : sve_mem_cldnf_si<0b1100, "ldnf1sb", Z_d, ZPR64>;
+ defm LDNF1SB_S_IMM : sve_mem_cldnf_si<0b1101, "ldnf1sb", Z_s, ZPR32>;
+ defm LDNF1SB_H_IMM : sve_mem_cldnf_si<0b1110, "ldnf1sb", Z_h, ZPR16>;
+ defm LDNF1D_IMM : sve_mem_cldnf_si<0b1111, "ldnf1d", Z_d, ZPR64>;
+
// LD(2|3|4) structured loads with reg+immediate
defm LD2B_IMM : sve_mem_eld_si<0b00, 0b01, ZZ_b, "ld2b", simm4Scale2MulVl>;
defm LD3B_IMM : sve_mem_eld_si<0b00, 0b10, ZZZ_b, "ld3b", simm4Scale3MulVl>;
Modified: llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td?rev=330583&r1=330582&r2=330583&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td Mon Apr 23 05:43:19 2018
@@ -712,6 +712,10 @@ multiclass sve_mem_cld_ss<bits<4> dtype,
}
+multiclass sve_mem_cldnf_si<bits<4> dtype, string asm, RegisterOperand listty,
+ ZPRRegOp zprty>
+: sve_mem_cld_si_base<dtype, 1, asm, listty, zprty>;
+
class sve_mem_eld_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
string asm, Operand immtype>
: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm4),
Added: llvm/trunk/test/MC/AArch64/SVE/ldnf1b-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldnf1b-diagnostics.s?rev=330583&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldnf1b-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ldnf1b-diagnostics.s Mon Apr 23 05:43:19 2018
@@ -0,0 +1,87 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-8, 7].
+
+ldnf1b z23.b, p0/z, [x13, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1b z23.b, p0/z, [x13, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1b z29.b, p0/z, [x3, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1b z29.b, p0/z, [x3, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1b z21.h, p4/z, [x17, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1b z21.h, p4/z, [x17, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1b z10.h, p5/z, [x16, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1b z10.h, p5/z, [x16, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1b z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1b z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1b z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1b z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1b z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1b z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1b z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1b z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+ldnf1b z27.b, p8/z, [x29, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ldnf1b z27.b, p8/z, [x29, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1b z9.h, p8/z, [x25, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ldnf1b z9.h, p8/z, [x25, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1b z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ldnf1b z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1b z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ldnf1b z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+ldnf1b { }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: ldnf1b { }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1b { z1.b, z2.b }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ldnf1b { z1.b, z2.b }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1b { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ldnf1b { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/ldnf1b.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldnf1b.s?rev=330583&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldnf1b.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ldnf1b.s Mon Apr 23 05:43:19 2018
@@ -0,0 +1,104 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ldnf1b z0.b, p0/z, [x0]
+// CHECK-INST: ldnf1b { z0.b }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x10,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 10 a4 <unknown>
+
+ldnf1b z0.h, p0/z, [x0]
+// CHECK-INST: ldnf1b { z0.h }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x30,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 30 a4 <unknown>
+
+ldnf1b z0.s, p0/z, [x0]
+// CHECK-INST: ldnf1b { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x50,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 50 a4 <unknown>
+
+ldnf1b z0.d, p0/z, [x0]
+// CHECK-INST: ldnf1b { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x70,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 70 a4 <unknown>
+
+ldnf1b { z0.b }, p0/z, [x0]
+// CHECK-INST: ldnf1b { z0.b }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x10,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 10 a4 <unknown>
+
+ldnf1b { z0.h }, p0/z, [x0]
+// CHECK-INST: ldnf1b { z0.h }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x30,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 30 a4 <unknown>
+
+ldnf1b { z0.s }, p0/z, [x0]
+// CHECK-INST: ldnf1b { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x50,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 50 a4 <unknown>
+
+ldnf1b { z0.d }, p0/z, [x0]
+// CHECK-INST: ldnf1b { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x70,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 70 a4 <unknown>
+
+ldnf1b { z31.b }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ldnf1b { z31.b }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x1f,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 1f a4 <unknown>
+
+ldnf1b { z21.b }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ldnf1b { z21.b }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x15,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 15 a4 <unknown>
+
+ldnf1b { z31.h }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ldnf1b { z31.h }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x3f,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 3f a4 <unknown>
+
+ldnf1b { z21.h }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ldnf1b { z21.h }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x35,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 35 a4 <unknown>
+
+ldnf1b { z31.s }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ldnf1b { z31.s }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x5f,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 5f a4 <unknown>
+
+ldnf1b { z21.s }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ldnf1b { z21.s }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x55,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 55 a4 <unknown>
+
+ldnf1b { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ldnf1b { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x7f,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 7f a4 <unknown>
+
+ldnf1b { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ldnf1b { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x75,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 75 a4 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/ldnf1d-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldnf1d-diagnostics.s?rev=330583&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldnf1d-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ldnf1d-diagnostics.s Mon Apr 23 05:43:19 2018
@@ -0,0 +1,42 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-8, 7].
+
+ldnf1d z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1d z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1d z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1d z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+ldnf1d z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ldnf1d z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+ldnf1d { }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: ldnf1d { }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1d { z1.d, z2.d }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ldnf1d { z1.d, z2.d }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1d { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ldnf1d { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/ldnf1d.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldnf1d.s?rev=330583&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldnf1d.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ldnf1d.s Mon Apr 23 05:43:19 2018
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ldnf1d z0.d, p0/z, [x0]
+// CHECK-INST: ldnf1d { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xf0,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 f0 a5 <unknown>
+
+ldnf1d { z0.d }, p0/z, [x0]
+// CHECK-INST: ldnf1d { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xf0,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 f0 a5 <unknown>
+
+ldnf1d { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ldnf1d { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0xff,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf ff a5 <unknown>
+
+ldnf1d { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ldnf1d { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0xf5,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 f5 a5 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/ldnf1h-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldnf1h-diagnostics.s?rev=330583&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldnf1h-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ldnf1h-diagnostics.s Mon Apr 23 05:43:19 2018
@@ -0,0 +1,72 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-8, 7].
+
+ldnf1h z21.h, p4/z, [x17, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1h z21.h, p4/z, [x17, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1h z10.h, p5/z, [x16, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1h z10.h, p5/z, [x16, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1h z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1h z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1h z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1h z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1h z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1h z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1h z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1h z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+ldnf1h z9.h, p8/z, [x25, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ldnf1h z9.h, p8/z, [x25, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1h z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ldnf1h z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1h z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ldnf1h z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+ldnf1h { }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: ldnf1h { }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1h { z1.h, z2.h }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ldnf1h { z1.h, z2.h }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1h { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ldnf1h { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/ldnf1h.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldnf1h.s?rev=330583&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldnf1h.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ldnf1h.s Mon Apr 23 05:43:19 2018
@@ -0,0 +1,80 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ldnf1h z0.h, p0/z, [x0]
+// CHECK-INST: ldnf1h { z0.h }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xb0,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 b0 a4 <unknown>
+
+ldnf1h z0.s, p0/z, [x0]
+// CHECK-INST: ldnf1h { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xd0,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 d0 a4 <unknown>
+
+ldnf1h z0.d, p0/z, [x0]
+// CHECK-INST: ldnf1h { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xf0,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 f0 a4 <unknown>
+
+ldnf1h { z0.h }, p0/z, [x0]
+// CHECK-INST: ldnf1h { z0.h }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xb0,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 b0 a4 <unknown>
+
+ldnf1h { z0.s }, p0/z, [x0]
+// CHECK-INST: ldnf1h { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xd0,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 d0 a4 <unknown>
+
+ldnf1h { z0.d }, p0/z, [x0]
+// CHECK-INST: ldnf1h { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xf0,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 f0 a4 <unknown>
+
+ldnf1h { z31.h }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ldnf1h { z31.h }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0xbf,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf bf a4 <unknown>
+
+ldnf1h { z21.h }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ldnf1h { z21.h }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0xb5,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 b5 a4 <unknown>
+
+ldnf1h { z31.s }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ldnf1h { z31.s }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0xdf,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf df a4 <unknown>
+
+ldnf1h { z21.s }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ldnf1h { z21.s }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0xd5,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 d5 a4 <unknown>
+
+ldnf1h { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ldnf1h { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0xff,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf ff a4 <unknown>
+
+ldnf1h { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ldnf1h { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0xf5,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 f5 a4 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/ldnf1sb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldnf1sb-diagnostics.s?rev=330583&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldnf1sb-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ldnf1sb-diagnostics.s Mon Apr 23 05:43:19 2018
@@ -0,0 +1,86 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid operand (.b)
+
+ldnf1sb z23.b, p0/z, [x13, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ldnf1sb z23.b, p0/z, [x13, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1sb z29.b, p0/z, [x3, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ldnf1sb z29.b, p0/z, [x3, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-8, 7].
+
+ldnf1sb z21.h, p4/z, [x17, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1sb z21.h, p4/z, [x17, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1sb z10.h, p5/z, [x16, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1sb z10.h, p5/z, [x16, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1sb z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1sb z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1sb z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1sb z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1sb z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1sb z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1sb z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1sb z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+ldnf1sb z9.h, p8/z, [x25, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ldnf1sb z9.h, p8/z, [x25, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1sb z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ldnf1sb z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1sb z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ldnf1sb z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+ldnf1sb { }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: ldnf1sb { }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1sb { z1.h, z2.h }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ldnf1sb { z1.h, z2.h }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1sb { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ldnf1sb { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/ldnf1sb.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldnf1sb.s?rev=330583&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldnf1sb.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ldnf1sb.s Mon Apr 23 05:43:19 2018
@@ -0,0 +1,80 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ldnf1sb z0.h, p0/z, [x0]
+// CHECK-INST: ldnf1sb { z0.h }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xd0,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 d0 a5 <unknown>
+
+ldnf1sb z0.s, p0/z, [x0]
+// CHECK-INST: ldnf1sb { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xb0,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 b0 a5 <unknown>
+
+ldnf1sb z0.d, p0/z, [x0]
+// CHECK-INST: ldnf1sb { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x90,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 90 a5 <unknown>
+
+ldnf1sb { z0.h }, p0/z, [x0]
+// CHECK-INST: ldnf1sb { z0.h }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xd0,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 d0 a5 <unknown>
+
+ldnf1sb { z0.s }, p0/z, [x0]
+// CHECK-INST: ldnf1sb { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xb0,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 b0 a5 <unknown>
+
+ldnf1sb { z0.d }, p0/z, [x0]
+// CHECK-INST: ldnf1sb { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x90,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 90 a5 <unknown>
+
+ldnf1sb { z31.h }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ldnf1sb { z31.h }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0xdf,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf df a5 <unknown>
+
+ldnf1sb { z21.h }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ldnf1sb { z21.h }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0xd5,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 d5 a5 <unknown>
+
+ldnf1sb { z31.s }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ldnf1sb { z31.s }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0xbf,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf bf a5 <unknown>
+
+ldnf1sb { z21.s }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ldnf1sb { z21.s }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0xb5,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 b5 a5 <unknown>
+
+ldnf1sb { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ldnf1sb { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x9f,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 9f a5 <unknown>
+
+ldnf1sb { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ldnf1sb { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x95,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 95 a5 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/ldnf1sh-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldnf1sh-diagnostics.s?rev=330583&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldnf1sh-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ldnf1sh-diagnostics.s Mon Apr 23 05:43:19 2018
@@ -0,0 +1,71 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid operand (.h)
+
+ldnf1sh z23.h, p0/z, [x13, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ldnf1sh z23.h, p0/z, [x13, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1sh z29.h, p0/z, [x3, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ldnf1sh z29.h, p0/z, [x3, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-8, 7].
+
+ldnf1sh z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1sh z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1sh z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1sh z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1sh z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1sh z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1sh z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1sh z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+ldnf1sh z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ldnf1sh z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1sh z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ldnf1sh z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+ldnf1sh { }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: ldnf1sh { }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1sh { z1.s, z2.s }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ldnf1sh { z1.s, z2.s }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1sh { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ldnf1sh { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/ldnf1sh.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldnf1sh.s?rev=330583&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldnf1sh.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ldnf1sh.s Mon Apr 23 05:43:19 2018
@@ -0,0 +1,56 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ldnf1sh z0.s, p0/z, [x0]
+// CHECK-INST: ldnf1sh { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x30,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 30 a5 <unknown>
+
+ldnf1sh z0.d, p0/z, [x0]
+// CHECK-INST: ldnf1sh { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x10,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 10 a5 <unknown>
+
+ldnf1sh { z0.s }, p0/z, [x0]
+// CHECK-INST: ldnf1sh { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x30,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 30 a5 <unknown>
+
+ldnf1sh { z0.d }, p0/z, [x0]
+// CHECK-INST: ldnf1sh { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x10,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 10 a5 <unknown>
+
+ldnf1sh { z31.s }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ldnf1sh { z31.s }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x3f,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 3f a5 <unknown>
+
+ldnf1sh { z21.s }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ldnf1sh { z21.s }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x35,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 35 a5 <unknown>
+
+ldnf1sh { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ldnf1sh { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x1f,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 1f a5 <unknown>
+
+ldnf1sh { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ldnf1sh { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x15,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 15 a5 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/ldnf1sw-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldnf1sw-diagnostics.s?rev=330583&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldnf1sw-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ldnf1sw-diagnostics.s Mon Apr 23 05:43:19 2018
@@ -0,0 +1,56 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid operand (.s)
+
+ldnf1sw z23.s, p0/z, [x13, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ldnf1sw z23.s, p0/z, [x13, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1sw z29.s, p0/z, [x3, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ldnf1sw z29.s, p0/z, [x3, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-8, 7].
+
+ldnf1sw z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1sw z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1sw z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1sw z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+ldnf1sw z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ldnf1sw z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+ldnf1sw { }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: ldnf1sw { }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1sw { z1.d, z2.d }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ldnf1sw { z1.d, z2.d }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1sw { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ldnf1sw { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/ldnf1sw.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldnf1sw.s?rev=330583&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldnf1sw.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ldnf1sw.s Mon Apr 23 05:43:19 2018
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ldnf1sw z0.d, p0/z, [x0]
+// CHECK-INST: ldnf1sw { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x90,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 90 a4 <unknown>
+
+ldnf1sw { z0.d }, p0/z, [x0]
+// CHECK-INST: ldnf1sw { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x90,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 90 a4 <unknown>
+
+ldnf1sw { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ldnf1sw { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x9f,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 9f a4 <unknown>
+
+ldnf1sw { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ldnf1sw { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x95,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 95 a4 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/ldnf1w-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldnf1w-diagnostics.s?rev=330583&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldnf1w-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ldnf1w-diagnostics.s Mon Apr 23 05:43:19 2018
@@ -0,0 +1,57 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-8, 7].
+
+ldnf1w z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1w z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1w z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1w z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1w z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1w z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1w z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ldnf1w z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+ldnf1w z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ldnf1w z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1w z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ldnf1w z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+ldnf1w { }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: ldnf1w { }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1w { z1.s, z2.s }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ldnf1w { z1.s, z2.s }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldnf1w { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ldnf1w { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/ldnf1w.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ldnf1w.s?rev=330583&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldnf1w.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ldnf1w.s Mon Apr 23 05:43:19 2018
@@ -0,0 +1,56 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ldnf1w z0.s, p0/z, [x0]
+// CHECK-INST: ldnf1w { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x50,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 50 a5 <unknown>
+
+ldnf1w z0.d, p0/z, [x0]
+// CHECK-INST: ldnf1w { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x70,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 70 a5 <unknown>
+
+ldnf1w { z0.s }, p0/z, [x0]
+// CHECK-INST: ldnf1w { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x50,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 50 a5 <unknown>
+
+ldnf1w { z0.d }, p0/z, [x0]
+// CHECK-INST: ldnf1w { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x70,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 70 a5 <unknown>
+
+ldnf1w { z31.s }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ldnf1w { z31.s }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x5f,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 5f a5 <unknown>
+
+ldnf1w { z21.s }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ldnf1w { z21.s }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x55,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 55 a5 <unknown>
+
+ldnf1w { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ldnf1w { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x7f,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 7f a5 <unknown>
+
+ldnf1w { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ldnf1w { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x75,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 75 a5 <unknown>
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