[llvm] r330565 - [AArch64][SVE] Asm: Support for structured ST2, ST3 and ST4 (scalar+imm) store instructions.
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 23 00:50:35 PDT 2018
Author: s.desmalen
Date: Mon Apr 23 00:50:35 2018
New Revision: 330565
URL: http://llvm.org/viewvc/llvm-project?rev=330565&view=rev
Log:
[AArch64][SVE] Asm: Support for structured ST2, ST3 and ST4 (scalar+imm) store instructions.
Reviewers: fhahn, rengolin, javed.absar, SjoerdMeijer, t.p.northover, echristo, evandro, huntergr
Reviewed By: rengolin
Subscribers: tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45681
Added:
llvm/trunk/test/MC/AArch64/SVE/st2b-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/st2b.s
llvm/trunk/test/MC/AArch64/SVE/st2d-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/st2d.s
llvm/trunk/test/MC/AArch64/SVE/st2h-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/st2h.s
llvm/trunk/test/MC/AArch64/SVE/st2w-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/st2w.s
llvm/trunk/test/MC/AArch64/SVE/st3b-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/st3b.s
llvm/trunk/test/MC/AArch64/SVE/st3d-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/st3d.s
llvm/trunk/test/MC/AArch64/SVE/st3h-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/st3h.s
llvm/trunk/test/MC/AArch64/SVE/st3w-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/st3w.s
llvm/trunk/test/MC/AArch64/SVE/st4b-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/st4b.s
llvm/trunk/test/MC/AArch64/SVE/st4d-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/st4d.s
llvm/trunk/test/MC/AArch64/SVE/st4h-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/st4h.s
llvm/trunk/test/MC/AArch64/SVE/st4w-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/st4w.s
Modified:
llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
Modified: llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td?rev=330565&r1=330564&r2=330565&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td Mon Apr 23 00:50:35 2018
@@ -82,6 +82,20 @@ let Predicates = [HasSVE] in {
defm ST1W_D_IMM : sve_mem_cst_si<0b10, 0b11, "st1w", Z_d, ZPR64>;
defm ST1D_IMM : sve_mem_cst_si<0b11, 0b11, "st1d", Z_d, ZPR64>;
+ // ST{2,3,4}{B,H,W,D} with immediate
+ defm ST2B_IMM : sve_mem_est_si<0b00, 0b01, ZZ_b, "st2b", simm4Scale2MulVl>;
+ defm ST3B_IMM : sve_mem_est_si<0b00, 0b10, ZZZ_b, "st3b", simm4Scale3MulVl>;
+ defm ST4B_IMM : sve_mem_est_si<0b00, 0b11, ZZZZ_b, "st4b", simm4Scale4MulVl>;
+ defm ST2H_IMM : sve_mem_est_si<0b01, 0b01, ZZ_h, "st2h", simm4Scale2MulVl>;
+ defm ST3H_IMM : sve_mem_est_si<0b01, 0b10, ZZZ_h, "st3h", simm4Scale3MulVl>;
+ defm ST4H_IMM : sve_mem_est_si<0b01, 0b11, ZZZZ_h, "st4h", simm4Scale4MulVl>;
+ defm ST2W_IMM : sve_mem_est_si<0b10, 0b01, ZZ_s, "st2w", simm4Scale2MulVl>;
+ defm ST3W_IMM : sve_mem_est_si<0b10, 0b10, ZZZ_s, "st3w", simm4Scale3MulVl>;
+ defm ST4W_IMM : sve_mem_est_si<0b10, 0b11, ZZZZ_s, "st4w", simm4Scale4MulVl>;
+ defm ST2D_IMM : sve_mem_est_si<0b11, 0b01, ZZ_d, "st2d", simm4Scale2MulVl>;
+ defm ST3D_IMM : sve_mem_est_si<0b11, 0b10, ZZZ_d, "st3d", simm4Scale3MulVl>;
+ defm ST4D_IMM : sve_mem_est_si<0b11, 0b11, ZZZZ_d, "st4d", simm4Scale4MulVl>;
+
defm ZIP1_ZZZ : sve_int_perm_bin_perm_zz<0b000, "zip1">;
defm ZIP2_ZZZ : sve_int_perm_bin_perm_zz<0b001, "zip2">;
Modified: llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td?rev=330565&r1=330564&r2=330565&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td Mon Apr 23 00:50:35 2018
@@ -571,6 +571,37 @@ multiclass sve_mem_cst_si<bits<2> msz, b
(!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
}
+class sve_mem_est_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
+ string asm, Operand immtype>
+: I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm4),
+ asm, "\t$Zt, $Pg, [$Rn, $imm4, mul vl]",
+ "",
+ []>, Sched<[]> {
+ bits<3> Pg;
+ bits<5> Rn;
+ bits<5> Zt;
+ bits<4> imm4;
+ let Inst{31-25} = 0b1110010;
+ let Inst{24-23} = sz;
+ let Inst{22-21} = nregs;
+ let Inst{20} = 1;
+ let Inst{19-16} = imm4;
+ let Inst{15-13} = 0b111;
+ let Inst{12-10} = Pg;
+ let Inst{9-5} = Rn;
+ let Inst{4-0} = Zt;
+
+ let mayStore = 1;
+}
+
+multiclass sve_mem_est_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
+ string asm, Operand immtype> {
+ def NAME : sve_mem_est_si<sz, nregs, VecList, asm, immtype>;
+
+ def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]",
+ (!cast<Instruction>(NAME) VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
+}
+
//===----------------------------------------------------------------------===//
// SVE Permute - Predicates Group
//===----------------------------------------------------------------------===//
Added: llvm/trunk/test/MC/AArch64/SVE/st2b-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st2b-diagnostics.s?rev=330565&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st2b-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/st2b-diagnostics.s Mon Apr 23 00:50:35 2018
@@ -0,0 +1,67 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-16, 14].
+
+st2b {z12.b, z13.b}, p4, [x12, #-18, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [-16, 14].
+// CHECK-NEXT: st2b {z12.b, z13.b}, p4, [x12, #-18, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st2b {z7.b, z8.b}, p3, [x1, #16, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [-16, 14].
+// CHECK-NEXT: st2b {z7.b, z8.b}, p3, [x1, #16, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Immediate not a multiple of two.
+
+st2b {z12.b, z13.b}, p4, [x12, #-7, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [-16, 14].
+// CHECK-NEXT: st2b {z12.b, z13.b}, p4, [x12, #-7, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st2b {z7.b, z8.b}, p3, [x1, #5, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [-16, 14].
+// CHECK-NEXT: st2b {z7.b, z8.b}, p3, [x1, #5, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// error: restricted predicate has range [0, 7].
+
+st2b {z2.b, z3.b}, p8, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: st2b {z2.b, z3.b}, p8, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+st2b { }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: st2b { }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st2b { z0.b, z1.b, z2.b }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: st2b { z0.b, z1.b, z2.b }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st2b { z0.b, z1.h }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
+// CHECK-NEXT: st2b { z0.b, z1.h }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st2b { z0.b, z2.b }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: st2b { z0.b, z2.b }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st2b { v0.2d, v1.2d }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: st2b { v0.2d, v1.2d }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/st2b.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st2b.s?rev=330565&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st2b.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/st2b.s Mon Apr 23 00:50:35 2018
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+st2b { z0.b, z1.b }, p0, [x0]
+// CHECK-INST: st2b { z0.b, z1.b }, p0, [x0]
+// CHECK-ENCODING: [0x00,0xe0,0x30,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 30 e4 <unknown>
+
+st2b { z23.b, z24.b }, p3, [x13, #-16, mul vl]
+// CHECK-INST: st2b { z23.b, z24.b }, p3, [x13, #-16, mul vl]
+// CHECK-ENCODING: [0xb7,0xed,0x38,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 ed 38 e4 <unknown>
+
+st2b { z21.b, z22.b }, p5, [x10, #10, mul vl]
+// CHECK-INST: st2b { z21.b, z22.b }, p5, [x10, #10, mul vl]
+// CHECK-ENCODING: [0x55,0xf5,0x35,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 f5 35 e4 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/st2d-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st2d-diagnostics.s?rev=330565&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st2d-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/st2d-diagnostics.s Mon Apr 23 00:50:35 2018
@@ -0,0 +1,67 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-16, 14].
+
+st2d {z12.d, z13.d}, p4, [x12, #-18, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [-16, 14].
+// CHECK-NEXT: st2d {z12.d, z13.d}, p4, [x12, #-18, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st2d {z7.d, z8.d}, p3, [x1, #16, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [-16, 14].
+// CHECK-NEXT: st2d {z7.d, z8.d}, p3, [x1, #16, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Immediate not a multiple of two.
+
+st2d {z12.d, z13.d}, p4, [x12, #-7, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [-16, 14].
+// CHECK-NEXT: st2d {z12.d, z13.d}, p4, [x12, #-7, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st2d {z7.d, z8.d}, p3, [x1, #5, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [-16, 14].
+// CHECK-NEXT: st2d {z7.d, z8.d}, p3, [x1, #5, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// error: restricted predicate has range [0, 7].
+
+st2d {z2.d, z3.d}, p8, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: st2d {z2.d, z3.d}, p8, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+st2d { }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: st2d { }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st2d { z0.d, z1.d, z2.d }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: st2d { z0.d, z1.d, z2.d }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st2d { z0.d, z1.b }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
+// CHECK-NEXT: st2d { z0.d, z1.b }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st2d { z0.d, z2.d }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: st2d { z0.d, z2.d }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st2d { v0.2d, v1.2d }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: st2d { v0.2d, v1.2d }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/st2d.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st2d.s?rev=330565&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st2d.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/st2d.s Mon Apr 23 00:50:35 2018
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+st2d { z0.d, z1.d }, p0, [x0]
+// CHECK-INST: st2d { z0.d, z1.d }, p0, [x0]
+// CHECK-ENCODING: [0x00,0xe0,0xb0,0xe5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 b0 e5 <unknown>
+
+st2d { z23.d, z24.d }, p3, [x13, #-16, mul vl]
+// CHECK-INST: st2d { z23.d, z24.d }, p3, [x13, #-16, mul vl]
+// CHECK-ENCODING: [0xb7,0xed,0xb8,0xe5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 ed b8 e5 <unknown>
+
+st2d { z21.d, z22.d }, p5, [x10, #10, mul vl]
+// CHECK-INST: st2d { z21.d, z22.d }, p5, [x10, #10, mul vl]
+// CHECK-ENCODING: [0x55,0xf5,0xb5,0xe5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 f5 b5 e5 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/st2h-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st2h-diagnostics.s?rev=330565&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st2h-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/st2h-diagnostics.s Mon Apr 23 00:50:35 2018
@@ -0,0 +1,67 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-16, 14].
+
+st2h {z12.h, z13.h}, p4, [x12, #-18, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [-16, 14].
+// CHECK-NEXT: st2h {z12.h, z13.h}, p4, [x12, #-18, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st2h {z7.h, z8.h}, p3, [x1, #16, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [-16, 14].
+// CHECK-NEXT: st2h {z7.h, z8.h}, p3, [x1, #16, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Immediate not a multiple of two.
+
+st2h {z12.h, z13.h}, p4, [x12, #-7, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [-16, 14].
+// CHECK-NEXT: st2h {z12.h, z13.h}, p4, [x12, #-7, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st2h {z7.h, z8.h}, p3, [x1, #5, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [-16, 14].
+// CHECK-NEXT: st2h {z7.h, z8.h}, p3, [x1, #5, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// error: restricted predicate has range [0, 7].
+
+st2h {z2.h, z3.h}, p8, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: st2h {z2.h, z3.h}, p8, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+st2h { }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: st2h { }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st2h { z0.h, z1.h, z2.h }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: st2h { z0.h, z1.h, z2.h }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st2h { z0.h, z1.s }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
+// CHECK-NEXT: st2h { z0.h, z1.s }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st2h { z0.h, z2.h }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: st2h { z0.h, z2.h }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st2h { v0.2d, v1.2d }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: st2h { v0.2d, v1.2d }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/st2h.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st2h.s?rev=330565&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st2h.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/st2h.s Mon Apr 23 00:50:35 2018
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+st2h { z0.h, z1.h }, p0, [x0]
+// CHECK-INST: st2h { z0.h, z1.h }, p0, [x0]
+// CHECK-ENCODING: [0x00,0xe0,0xb0,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 b0 e4 <unknown>
+
+st2h { z23.h, z24.h }, p3, [x13, #-16, mul vl]
+// CHECK-INST: st2h { z23.h, z24.h }, p3, [x13, #-16, mul vl]
+// CHECK-ENCODING: [0xb7,0xed,0xb8,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 ed b8 e4 <unknown>
+
+st2h { z21.h, z22.h }, p5, [x10, #10, mul vl]
+// CHECK-INST: st2h { z21.h, z22.h }, p5, [x10, #10, mul vl]
+// CHECK-ENCODING: [0x55,0xf5,0xb5,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 f5 b5 e4 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/st2w-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st2w-diagnostics.s?rev=330565&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st2w-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/st2w-diagnostics.s Mon Apr 23 00:50:35 2018
@@ -0,0 +1,67 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-16, 14].
+
+st2w {z12.s, z13.s}, p4, [x12, #-18, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [-16, 14].
+// CHECK-NEXT: st2w {z12.s, z13.s}, p4, [x12, #-18, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st2w {z7.s, z8.s}, p3, [x1, #16, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [-16, 14].
+// CHECK-NEXT: st2w {z7.s, z8.s}, p3, [x1, #16, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Immediate not a multiple of two.
+
+st2w {z12.s, z13.s}, p4, [x12, #-7, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [-16, 14].
+// CHECK-NEXT: st2w {z12.s, z13.s}, p4, [x12, #-7, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st2w {z7.s, z8.s}, p3, [x1, #5, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [-16, 14].
+// CHECK-NEXT: st2w {z7.s, z8.s}, p3, [x1, #5, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// error: restricted predicate has range [0, 7].
+
+st2w {z2.s, z3.s}, p8, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: st2w {z2.s, z3.s}, p8, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+st2w { }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: st2w { }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st2w { z0.s, z1.s, z2.s }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: st2w { z0.s, z1.s, z2.s }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st2w { z0.s, z1.d }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
+// CHECK-NEXT: st2w { z0.s, z1.d }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st2w { z0.s, z2.s }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: st2w { z0.s, z2.s }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st2w { v0.2d, v1.2d }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: st2w { v0.2d, v1.2d }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/st2w.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st2w.s?rev=330565&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st2w.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/st2w.s Mon Apr 23 00:50:35 2018
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+st2w { z0.s, z1.s }, p0, [x0]
+// CHECK-INST: st2w { z0.s, z1.s }, p0, [x0]
+// CHECK-ENCODING: [0x00,0xe0,0x30,0xe5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 30 e5 <unknown>
+
+st2w { z23.s, z24.s }, p3, [x13, #-16, mul vl]
+// CHECK-INST: st2w { z23.s, z24.s }, p3, [x13, #-16, mul vl]
+// CHECK-ENCODING: [0xb7,0xed,0x38,0xe5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 ed 38 e5 <unknown>
+
+st2w { z21.s, z22.s }, p5, [x10, #10, mul vl]
+// CHECK-INST: st2w { z21.s, z22.s }, p5, [x10, #10, mul vl]
+// CHECK-ENCODING: [0x55,0xf5,0x35,0xe5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 f5 35 e5 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/st3b-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st3b-diagnostics.s?rev=330565&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st3b-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/st3b-diagnostics.s Mon Apr 23 00:50:35 2018
@@ -0,0 +1,67 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-24, 21].
+
+st3b {z12.b, z13.b, z14.b}, p4, [x12, #-27, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
+// CHECK-NEXT: st3b {z12.b, z13.b, z14.b}, p4, [x12, #-27, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st3b {z7.b, z8.b, z9.b}, p3, [x1, #24, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
+// CHECK-NEXT: st3b {z7.b, z8.b, z9.b}, p3, [x1, #24, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Immediate not a multiple of three.
+
+st3b {z12.b, z13.b, z14.b}, p4, [x12, #-7, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
+// CHECK-NEXT: st3b {z12.b, z13.b, z14.b}, p4, [x12, #-7, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st3b {z7.b, z8.b, z9.b}, p3, [x1, #5, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
+// CHECK-NEXT: st3b {z7.b, z8.b, z9.b}, p3, [x1, #5, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// error: restricted predicate has range [0, 7].
+
+st3b {z2.b, z3.b, z4.b}, p8, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: st3b {z2.b, z3.b, z4.b}, p8, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+st3b { }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: st3b { }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st3b { z0.b, z1.b, z2.b, z3.b }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: st3b { z0.b, z1.b, z2.b, z3.b }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st3b { z0.b, z1.b, z2.h }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
+// CHECK-NEXT: st3b { z0.b, z1.b, z2.h }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st3b { z0.b, z1.b, z3.b }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: st3b { z0.b, z1.b, z3.b }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st3b { v0.16b, v1.16b, v2.16b }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: st3b { v0.16b, v1.16b, v2.16b }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/st3b.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st3b.s?rev=330565&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st3b.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/st3b.s Mon Apr 23 00:50:35 2018
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+st3b { z0.b, z1.b, z2.b }, p0, [x0]
+// CHECK-INST: st3b { z0.b, z1.b, z2.b }, p0, [x0]
+// CHECK-ENCODING: [0x00,0xe0,0x50,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 50 e4 <unknown>
+
+st3b { z23.b, z24.b, z25.b }, p3, [x13, #-24, mul vl]
+// CHECK-INST: st3b { z23.b, z24.b, z25.b }, p3, [x13, #-24, mul vl]
+// CHECK-ENCODING: [0xb7,0xed,0x58,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 ed 58 e4 <unknown>
+
+st3b { z21.b, z22.b, z23.b }, p5, [x10, #15, mul vl]
+// CHECK-INST: st3b { z21.b, z22.b, z23.b }, p5, [x10, #15, mul vl]
+// CHECK-ENCODING: [0x55,0xf5,0x55,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 f5 55 e4 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/st3d-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st3d-diagnostics.s?rev=330565&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st3d-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/st3d-diagnostics.s Mon Apr 23 00:50:35 2018
@@ -0,0 +1,67 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-24, 21].
+
+st3d {z12.d, z13.d, z14.d}, p4, [x12, #-27, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
+// CHECK-NEXT: st3d {z12.d, z13.d, z14.d}, p4, [x12, #-27, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st3d {z7.d, z8.d, z9.d}, p3, [x1, #24, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
+// CHECK-NEXT: st3d {z7.d, z8.d, z9.d}, p3, [x1, #24, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Immediate not a multiple of three.
+
+st3d {z12.d, z13.d, z14.d}, p4, [x12, #-7, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
+// CHECK-NEXT: st3d {z12.d, z13.d, z14.d}, p4, [x12, #-7, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st3d {z7.d, z8.d, z9.d}, p3, [x1, #5, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
+// CHECK-NEXT: st3d {z7.d, z8.d, z9.d}, p3, [x1, #5, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// error: restricted predicate has range [0, 7].
+
+st3d {z2.d, z3.d, z4.d}, p8, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: st3d {z2.d, z3.d, z4.d}, p8, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+st3d { }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: st3d { }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st3d { z0.d, z1.d, z2.d, z3.d }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: st3d { z0.d, z1.d, z2.d, z3.d }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st3d { z0.d, z1.d, z2.b }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
+// CHECK-NEXT: st3d { z0.d, z1.d, z2.b }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st3d { z0.d, z1.d, z3.d }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: st3d { z0.d, z1.d, z3.d }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st3d { v0.2d, v1.2d, v2.2d }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: st3d { v0.2d, v1.2d, v2.2d }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/st3d.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st3d.s?rev=330565&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st3d.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/st3d.s Mon Apr 23 00:50:35 2018
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+st3d { z0.d, z1.d, z2.d }, p0, [x0]
+// CHECK-INST: st3d { z0.d, z1.d, z2.d }, p0, [x0]
+// CHECK-ENCODING: [0x00,0xe0,0xd0,0xe5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 d0 e5 <unknown>
+
+st3d { z23.d, z24.d, z25.d }, p3, [x13, #-24, mul vl]
+// CHECK-INST: st3d { z23.d, z24.d, z25.d }, p3, [x13, #-24, mul vl]
+// CHECK-ENCODING: [0xb7,0xed,0xd8,0xe5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 ed d8 e5 <unknown>
+
+st3d { z21.d, z22.d, z23.d }, p5, [x10, #15, mul vl]
+// CHECK-INST: st3d { z21.d, z22.d, z23.d }, p5, [x10, #15, mul vl]
+// CHECK-ENCODING: [0x55,0xf5,0xd5,0xe5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 f5 d5 e5 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/st3h-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st3h-diagnostics.s?rev=330565&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st3h-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/st3h-diagnostics.s Mon Apr 23 00:50:35 2018
@@ -0,0 +1,67 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-24, 21].
+
+st3h {z12.h, z13.h, z14.h}, p4, [x12, #-27, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
+// CHECK-NEXT: st3h {z12.h, z13.h, z14.h}, p4, [x12, #-27, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st3h {z7.h, z8.h, z9.h}, p3, [x1, #24, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
+// CHECK-NEXT: st3h {z7.h, z8.h, z9.h}, p3, [x1, #24, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Immediate not a multiple of three.
+
+st3h {z12.h, z13.h, z14.h}, p4, [x12, #-7, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
+// CHECK-NEXT: st3h {z12.h, z13.h, z14.h}, p4, [x12, #-7, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st3h {z7.h, z8.h, z9.h}, p3, [x1, #5, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
+// CHECK-NEXT: st3h {z7.h, z8.h, z9.h}, p3, [x1, #5, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// error: restricted predicate has range [0, 7].
+
+st3h {z2.h, z3.h, z4.h}, p8, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: st3h {z2.h, z3.h, z4.h}, p8, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+st3h { }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: st3h { }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st3h { z0.h, z1.h, z2.h, z3.h }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: st3h { z0.h, z1.h, z2.h, z3.h }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st3h { z0.h, z1.h, z2.s }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
+// CHECK-NEXT: st3h { z0.h, z1.h, z2.s }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st3h { z0.h, z1.h, z3.h }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: st3h { z0.h, z1.h, z3.h }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st3h { v0.8h, v1.8h, v2.8h }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: st3h { v0.8h, v1.8h, v2.8h }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/st3h.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st3h.s?rev=330565&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st3h.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/st3h.s Mon Apr 23 00:50:35 2018
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+st3h { z0.h, z1.h, z2.h }, p0, [x0]
+// CHECK-INST: st3h { z0.h, z1.h, z2.h }, p0, [x0]
+// CHECK-ENCODING: [0x00,0xe0,0xd0,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 d0 e4 <unknown>
+
+st3h { z23.h, z24.h, z25.h }, p3, [x13, #-24, mul vl]
+// CHECK-INST: st3h { z23.h, z24.h, z25.h }, p3, [x13, #-24, mul vl]
+// CHECK-ENCODING: [0xb7,0xed,0xd8,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 ed d8 e4 <unknown>
+
+st3h { z21.h, z22.h, z23.h }, p5, [x10, #15, mul vl]
+// CHECK-INST: st3h { z21.h, z22.h, z23.h }, p5, [x10, #15, mul vl]
+// CHECK-ENCODING: [0x55,0xf5,0xd5,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 f5 d5 e4 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/st3w-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st3w-diagnostics.s?rev=330565&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st3w-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/st3w-diagnostics.s Mon Apr 23 00:50:35 2018
@@ -0,0 +1,67 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-24, 21].
+
+st3w {z12.s, z13.s, z14.s}, p4, [x12, #-27, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
+// CHECK-NEXT: st3w {z12.s, z13.s, z14.s}, p4, [x12, #-27, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st3w {z7.s, z8.s, z9.s}, p3, [x1, #24, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
+// CHECK-NEXT: st3w {z7.s, z8.s, z9.s}, p3, [x1, #24, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Immediate not a multiple of three.
+
+st3w {z12.s, z13.s, z14.s}, p4, [x12, #-7, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
+// CHECK-NEXT: st3w {z12.s, z13.s, z14.s}, p4, [x12, #-7, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st3w {z7.s, z8.s, z9.s}, p3, [x1, #5, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
+// CHECK-NEXT: st3w {z7.s, z8.s, z9.s}, p3, [x1, #5, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// error: restricted predicate has range [0, 7].
+
+st3w {z2.s, z3.s, z4.s}, p8, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: st3w {z2.s, z3.s, z4.s}, p8, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+st3w { }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: st3w { }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st3w { z0.s, z1.s, z2.s, z3.s }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: st3w { z0.s, z1.s, z2.s, z3.s }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st3w { z0.s, z1.s, z2.d }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
+// CHECK-NEXT: st3w { z0.s, z1.s, z2.d }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st3w { z0.s, z1.s, z3.s }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: st3w { z0.s, z1.s, z3.s }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st3w { v0.4s, v1.4s, v2.4s }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: st3w { v0.4s, v1.4s, v2.4s }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/st3w.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st3w.s?rev=330565&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st3w.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/st3w.s Mon Apr 23 00:50:35 2018
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+st3w { z0.s, z1.s, z2.s }, p0, [x0]
+// CHECK-INST: st3w { z0.s, z1.s, z2.s }, p0, [x0]
+// CHECK-ENCODING: [0x00,0xe0,0x50,0xe5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 50 e5 <unknown>
+
+st3w { z23.s, z24.s, z25.s }, p3, [x13, #-24, mul vl]
+// CHECK-INST: st3w { z23.s, z24.s, z25.s }, p3, [x13, #-24, mul vl]
+// CHECK-ENCODING: [0xb7,0xed,0x58,0xe5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 ed 58 e5 <unknown>
+
+st3w { z21.s, z22.s, z23.s }, p5, [x10, #15, mul vl]
+// CHECK-INST: st3w { z21.s, z22.s, z23.s }, p5, [x10, #15, mul vl]
+// CHECK-ENCODING: [0x55,0xf5,0x55,0xe5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 f5 55 e5 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/st4b-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st4b-diagnostics.s?rev=330565&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st4b-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/st4b-diagnostics.s Mon Apr 23 00:50:35 2018
@@ -0,0 +1,67 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-32, 28].
+
+st4b {z12.b, z13.b, z14.b, z15.b}, p4, [x12, #-36, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].
+// CHECK-NEXT: st4b {z12.b, z13.b, z14.b, z15.b}, p4, [x12, #-36, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st4b {z7.b, z8.b, z9.b, z10.b}, p3, [x1, #32, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].
+// CHECK-NEXT: st4b {z7.b, z8.b, z9.b, z10.b}, p3, [x1, #32, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Immediate not a multiple of four.
+
+st4b {z12.b, z13.b, z14.b, z15.b}, p4, [x12, #-7, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].
+// CHECK-NEXT: st4b {z12.b, z13.b, z14.b, z15.b}, p4, [x12, #-7, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st4b {z7.b, z8.b, z9.b, z10.b}, p3, [x1, #5, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].
+// CHECK-NEXT: st4b {z7.b, z8.b, z9.b, z10.b}, p3, [x1, #5, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// error: restricted predicate has range [0, 7].
+
+st4b {z2.b, z3.b, z4.b, z5.b}, p8, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: st4b {z2.b, z3.b, z4.b, z5.b}, p8, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+st4b { }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: st4b { }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st4b { z0.b, z1.b, z2.b, z3.b, z4.b }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.b, z4.b }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st4b { z0.b, z1.b, z2.b, z3.h }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
+// CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.h }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st4b { z0.b, z1.b, z3.b, z5.b }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: st4b { z0.b, z1.b, z3.b, z5.b }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st4b { v0.16b, v1.16b, v2.16b }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: st4b { v0.16b, v1.16b, v2.16b }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/st4b.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st4b.s?rev=330565&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st4b.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/st4b.s Mon Apr 23 00:50:35 2018
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0]
+// CHECK-INST: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0]
+// CHECK-ENCODING: [0x00,0xe0,0x70,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 70 e4 <unknown>
+
+st4b { z23.b, z24.b, z25.b, z26.b }, p3, [x13, #-32, mul vl]
+// CHECK-INST: st4b { z23.b, z24.b, z25.b, z26.b }, p3, [x13, #-32, mul vl]
+// CHECK-ENCODING: [0xb7,0xed,0x78,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 ed 78 e4 <unknown>
+
+st4b { z21.b, z22.b, z23.b, z24.b }, p5, [x10, #20, mul vl]
+// CHECK-INST: st4b { z21.b, z22.b, z23.b, z24.b }, p5, [x10, #20, mul vl]
+// CHECK-ENCODING: [0x55,0xf5,0x75,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 f5 75 e4 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/st4d-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st4d-diagnostics.s?rev=330565&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st4d-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/st4d-diagnostics.s Mon Apr 23 00:50:35 2018
@@ -0,0 +1,67 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-32, 28].
+
+st4d {z12.d, z13.d, z14.d, z15.d}, p4, [x12, #-36, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].
+// CHECK-NEXT: st4d {z12.d, z13.d, z14.d, z15.d}, p4, [x12, #-36, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st4d {z7.d, z8.d, z9.d, z10.d}, p3, [x1, #32, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].
+// CHECK-NEXT: st4d {z7.d, z8.d, z9.d, z10.d}, p3, [x1, #32, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Immediate not a multiple of four.
+
+st4d {z12.d, z13.d, z14.d, z15.d}, p4, [x12, #-7, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].
+// CHECK-NEXT: st4d {z12.d, z13.d, z14.d, z15.d}, p4, [x12, #-7, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st4d {z7.d, z8.d, z9.d, z10.d}, p3, [x1, #5, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].
+// CHECK-NEXT: st4d {z7.d, z8.d, z9.d, z10.d}, p3, [x1, #5, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// error: restricted predicate has range [0, 7].
+
+st4d {z2.d, z3.d, z4.d, z5.d}, p8, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: st4d {z2.d, z3.d, z4.d, z5.d}, p8, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+st4d { }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: st4d { }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st4d { z0.d, z1.d, z2.d, z3.d, z4.d }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: st4d { z0.d, z1.d, z2.d, z3.d, z4.d }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st4d { z0.d, z1.d, z2.d, z3.b }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
+// CHECK-NEXT: st4d { z0.d, z1.d, z2.d, z3.b }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st4d { z0.d, z1.d, z3.d, z5.d }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: st4d { z0.d, z1.d, z3.d, z5.d }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st4d { v0.2d, v1.2d, v2.2d }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: st4d { v0.2d, v1.2d, v2.2d }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/st4d.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st4d.s?rev=330565&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st4d.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/st4d.s Mon Apr 23 00:50:35 2018
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0]
+// CHECK-INST: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0]
+// CHECK-ENCODING: [0x00,0xe0,0xf0,0xe5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 f0 e5 <unknown>
+
+st4d { z23.d, z24.d, z25.d, z26.d }, p3, [x13, #-32, mul vl]
+// CHECK-INST: st4d { z23.d, z24.d, z25.d, z26.d }, p3, [x13, #-32, mul vl]
+// CHECK-ENCODING: [0xb7,0xed,0xf8,0xe5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 ed f8 e5 <unknown>
+
+st4d { z21.d, z22.d, z23.d, z24.d }, p5, [x10, #20, mul vl]
+// CHECK-INST: st4d { z21.d, z22.d, z23.d, z24.d }, p5, [x10, #20, mul vl]
+// CHECK-ENCODING: [0x55,0xf5,0xf5,0xe5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 f5 f5 e5 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/st4h-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st4h-diagnostics.s?rev=330565&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st4h-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/st4h-diagnostics.s Mon Apr 23 00:50:35 2018
@@ -0,0 +1,67 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-32, 28].
+
+st4h {z12.h, z13.h, z14.h, z15.h}, p4, [x12, #-36, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].
+// CHECK-NEXT: st4h {z12.h, z13.h, z14.h, z15.h}, p4, [x12, #-36, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st4h {z7.h, z8.h, z9.h, z10.h}, p3, [x1, #32, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].
+// CHECK-NEXT: st4h {z7.h, z8.h, z9.h, z10.h}, p3, [x1, #32, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Immediate not a multiple of four.
+
+st4h {z12.h, z13.h, z14.h, z15.h}, p4, [x12, #-7, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].
+// CHECK-NEXT: st4h {z12.h, z13.h, z14.h, z15.h}, p4, [x12, #-7, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st4h {z7.h, z8.h, z9.h, z10.h}, p3, [x1, #5, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].
+// CHECK-NEXT: st4h {z7.h, z8.h, z9.h, z10.h}, p3, [x1, #5, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// error: restricted predicate has range [0, 7].
+
+st4h {z2.h, z3.h, z4.h, z5.h}, p8, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: st4h {z2.h, z3.h, z4.h, z5.h}, p8, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+st4h { }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: st4h { }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st4h { z0.h, z1.h, z2.h, z3.h, z4.h }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: st4h { z0.h, z1.h, z2.h, z3.h, z4.h }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st4h { z0.h, z1.h, z2.h, z3.s }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
+// CHECK-NEXT: st4h { z0.h, z1.h, z2.h, z3.s }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st4h { z0.h, z1.h, z3.h, z5.h }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: st4h { z0.h, z1.h, z3.h, z5.h }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st4h { v0.8h, v1.8h, v2.8h }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: st4h { v0.8h, v1.8h, v2.8h }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/st4h.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st4h.s?rev=330565&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st4h.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/st4h.s Mon Apr 23 00:50:35 2018
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0]
+// CHECK-INST: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0]
+// CHECK-ENCODING: [0x00,0xe0,0xf0,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 f0 e4 <unknown>
+
+st4h { z23.h, z24.h, z25.h, z26.h }, p3, [x13, #-32, mul vl]
+// CHECK-INST: st4h { z23.h, z24.h, z25.h, z26.h }, p3, [x13, #-32, mul vl]
+// CHECK-ENCODING: [0xb7,0xed,0xf8,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 ed f8 e4 <unknown>
+
+st4h { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl]
+// CHECK-INST: st4h { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl]
+// CHECK-ENCODING: [0x55,0xf5,0xf5,0xe4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 f5 f5 e4 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/st4w-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st4w-diagnostics.s?rev=330565&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st4w-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/st4w-diagnostics.s Mon Apr 23 00:50:35 2018
@@ -0,0 +1,67 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-32, 28].
+
+st4w {z12.s, z13.s, z14.s, z15.s}, p4, [x12, #-36, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].
+// CHECK-NEXT: st4w {z12.s, z13.s, z14.s, z15.s}, p4, [x12, #-36, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st4w {z7.s, z8.s, z9.s, z10.s}, p3, [x1, #32, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].
+// CHECK-NEXT: st4w {z7.s, z8.s, z9.s, z10.s}, p3, [x1, #32, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Immediate not a multiple of four.
+
+st4w {z12.s, z13.s, z14.s, z15.s}, p4, [x12, #-7, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].
+// CHECK-NEXT: st4w {z12.s, z13.s, z14.s, z15.s}, p4, [x12, #-7, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st4w {z7.s, z8.s, z9.s, z10.s}, p3, [x1, #5, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].
+// CHECK-NEXT: st4w {z7.s, z8.s, z9.s, z10.s}, p3, [x1, #5, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// error: restricted predicate has range [0, 7].
+
+st4w {z2.s, z3.s, z4.s, z5.s}, p8, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: st4w {z2.s, z3.s, z4.s, z5.s}, p8, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+st4w { }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: st4w { }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st4w { z0.s, z1.s, z2.s, z3.s, z4.s }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: st4w { z0.s, z1.s, z2.s, z3.s, z4.s }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st4w { z0.s, z1.s, z2.s, z3.d }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
+// CHECK-NEXT: st4w { z0.s, z1.s, z2.s, z3.d }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st4w { z0.s, z1.s, z3.s, z5.s }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: st4w { z0.s, z1.s, z3.s, z5.s }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st4w { v0.4s, v1.4s, v2.4s }, p0, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: st4w { v0.4s, v1.4s, v2.4s }, p0, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/st4w.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st4w.s?rev=330565&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st4w.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/st4w.s Mon Apr 23 00:50:35 2018
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0]
+// CHECK-INST: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0]
+// CHECK-ENCODING: [0x00,0xe0,0x70,0xe5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 70 e5 <unknown>
+
+st4w { z23.s, z24.s, z25.s, z26.s }, p3, [x13, #-32, mul vl]
+// CHECK-INST: st4w { z23.s, z24.s, z25.s, z26.s }, p3, [x13, #-32, mul vl]
+// CHECK-ENCODING: [0xb7,0xed,0x78,0xe5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 ed 78 e5 <unknown>
+
+st4w { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl]
+// CHECK-INST: st4w { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl]
+// CHECK-ENCODING: [0x55,0xf5,0x75,0xe5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 f5 75 e5 <unknown>
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