[llvm] r330558 - [X86][Znver1] Remove unnecessary BMI1 ANDN InstRW overrides.

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Sun Apr 22 14:37:08 2018
New Revision: 330558

URL: http://llvm.org/viewvc/llvm-project?rev=330558&view=rev
Log:
[X86][Znver1] Remove unnecessary BMI1 ANDN InstRW overrides.

Modified:
    llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td

Modified: llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td?rev=330558&r1=330557&r2=330558&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td Sun Apr 22 14:37:08 2018
@@ -532,12 +532,6 @@ def : InstRW<[WriteALULd],
              (instregex "(AND|OR|XOR)(8|16|32|64)m(r|i)",
               "(AND|OR|XOR)(8|16|32|64)mi8", "(AND|OR|XOR)64mi32")>;
 
-// ANDN.
-// r,r.
-def : InstRW<[WriteALU], (instregex "ANDN(32|64)rr")>;
-// r,m.
-def : InstRW<[WriteALULd, ReadAfterLd], (instregex "ANDN(32|64)rm")>;
-
 // Define ALU latency variants
 def ZnWriteALULat2 : SchedWriteRes<[ZnALU]> {
   let Latency = 2;