Author: rksimon
Date: Sat Apr 21 12:11:55 2018
New Revision: 330521
URL: http://llvm.org/viewvc/llvm-project?rev=330521&view=rev
Log:
[X86] Strip unnecessary vector integer math, shift-imm, extend, shuffle, pack/unpack instruction instrw overrides from scheduler models.
Modified:
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=330521&r1=330520&r2=330521&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Sat Apr 21 12:11:55 2018
@@ -328,16 +328,8 @@ def: InstRW<[BWWriteResGroup1], (instreg
"MMX_MOVD64grr",
"(V?)MOVPDI2DIrr",
"(V?)MOVPQIto64rr",
- "(V?)PSLLD(Y?)ri",
- "(V?)PSLLQ(Y?)ri",
"VPSLLVQ(Y?)rr",
- "(V?)PSLLW(Y?)ri",
- "(V?)PSRAD(Y?)ri",
- "(V?)PSRAW(Y?)ri",
- "(V?)PSRLD(Y?)ri",
- "(V?)PSRLQ(Y?)ri",
"VPSRLVQ(Y?)rr",
- "(V?)PSRLW(Y?)ri",
"VTESTPD(Y?)rr",
"VTESTPS(Y?)rr")>;
@@ -366,35 +358,11 @@ def: InstRW<[BWWriteResGroup3], (instreg
"(V?)MOVDI2PDIrr",
"(V?)MOVUPD(Y?)rr",
"(V?)MOVUPS(Y?)rr",
- "(V?)PALIGNR(Y?)rri",
"(V?)PBLENDW(Y?)rri",
"VPBROADCASTDrr",
"VPBROADCASTQrr",
- "(V?)PMOVSXBDrr",
- "(V?)PMOVSXBQrr",
- "(V?)PMOVSXBWrr",
- "(V?)PMOVSXDQrr",
- "(V?)PMOVSXWDrr",
- "(V?)PMOVSXWQrr",
- "(V?)PMOVZXBDrr",
- "(V?)PMOVZXBQrr",
- "(V?)PMOVZXBWrr",
- "(V?)PMOVZXDQrr",
- "(V?)PMOVZXWDrr",
- "(V?)PMOVZXWQrr",
- "(V?)PSHUFD(Y?)ri",
- "(V?)PSHUFHW(Y?)ri",
- "(V?)PSHUFLW(Y?)ri",
"(V?)PSLLDQ(Y?)ri",
- "(V?)PSRLDQ(Y?)ri",
- "(V?)PUNPCKHBW(Y?)rr",
- "(V?)PUNPCKHDQ(Y?)rr",
- "(V?)PUNPCKHQDQ(Y?)rr",
- "(V?)PUNPCKHWD(Y?)rr",
- "(V?)PUNPCKLBW(Y?)rr",
- "(V?)PUNPCKLDQ(Y?)rr",
- "(V?)PUNPCKLQDQ(Y?)rr",
- "(V?)PUNPCKLWD(Y?)rr")>;
+ "(V?)PSRLDQ(Y?)ri")>;
def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> {
let Latency = 1;
@@ -443,50 +411,7 @@ def: InstRW<[BWWriteResGroup7], (instreg
"BLSI(32|64)rr",
"BLSMSK(32|64)rr",
"BLSR(32|64)rr",
- "LEA(16|32|64)(_32)?r",
- "(V?)PABSB(Y?)rr",
- "(V?)PABSD(Y?)rr",
- "(V?)PABSW(Y?)rr",
- "(V?)PADDB(Y?)rr",
- "(V?)PADDD(Y?)rr",
- "(V?)PADDQ(Y?)rr",
- "(V?)PADDSB(Y?)rr",
- "(V?)PADDSW(Y?)rr",
- "(V?)PADDUSB(Y?)rr",
- "(V?)PADDUSW(Y?)rr",
- "(V?)PADDW(Y?)rr",
- "(V?)PAVGB(Y?)rr",
- "(V?)PAVGW(Y?)rr",
- "(V?)PCMPEQB(Y?)rr",
- "(V?)PCMPEQD(Y?)rr",
- "(V?)PCMPEQQ(Y?)rr",
- "(V?)PCMPEQW(Y?)rr",
- "(V?)PCMPGTB(Y?)rr",
- "(V?)PCMPGTD(Y?)rr",
- "(V?)PCMPGTW(Y?)rr",
- "(V?)PMAXSB(Y?)rr",
- "(V?)PMAXSD(Y?)rr",
- "(V?)PMAXSW(Y?)rr",
- "(V?)PMAXUB(Y?)rr",
- "(V?)PMAXUD(Y?)rr",
- "(V?)PMAXUW(Y?)rr",
- "(V?)PMINSB(Y?)rr",
- "(V?)PMINSD(Y?)rr",
- "(V?)PMINSW(Y?)rr",
- "(V?)PMINUB(Y?)rr",
- "(V?)PMINUD(Y?)rr",
- "(V?)PMINUW(Y?)rr",
- "(V?)PSIGNB(Y?)rr",
- "(V?)PSIGND(Y?)rr",
- "(V?)PSIGNW(Y?)rr",
- "(V?)PSUBB(Y?)rr",
- "(V?)PSUBD(Y?)rr",
- "(V?)PSUBQ(Y?)rr",
- "(V?)PSUBSB(Y?)rr",
- "(V?)PSUBSW(Y?)rr",
- "(V?)PSUBUSB(Y?)rr",
- "(V?)PSUBUSW(Y?)rr",
- "(V?)PSUBW(Y?)rr")>;
+ "LEA(16|32|64)(_32)?r")>;
def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> {
let Latency = 1;
@@ -958,16 +883,7 @@ def BWWriteResGroup47 : SchedWriteRes<[B
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[BWWriteResGroup47], (instregex "(V?)PCMPGTQ(Y?)rr",
- "(V?)PHMINPOSUWrr",
- "(V?)PMADDUBSW(Y?)rr",
- "(V?)PMADDWD(Y?)rr",
- "(V?)PMULDQ(Y?)rr",
- "(V?)PMULHRSW(Y?)rr",
- "(V?)PMULHUW(Y?)rr",
- "(V?)PMULHW(Y?)rr",
- "(V?)PMULLW(Y?)rr",
- "(V?)PMULUDQ(Y?)rr")>;
+def: InstRW<[BWWriteResGroup47], (instregex "(V?)PCMPGTQ(Y?)rr")>;
def BWWriteResGroup49 : SchedWriteRes<[BWPort23]> {
let Latency = 5;
@@ -1161,18 +1077,6 @@ def: InstRW<[BWWriteResGroup61], (instre
"(V?)PINSRDrm",
"(V?)PINSRQrm",
"(V?)PINSRWrm",
- "(V?)PMOVSXBDrm",
- "(V?)PMOVSXBQrm",
- "(V?)PMOVSXBWrm",
- "(V?)PMOVSXDQrm",
- "(V?)PMOVSXWDrm",
- "(V?)PMOVSXWQrm",
- "(V?)PMOVZXBDrm",
- "(V?)PMOVZXBQrm",
- "(V?)PMOVZXBWrm",
- "(V?)PMOVZXDQrm",
- "(V?)PMOVZXWDrm",
- "(V?)PMOVZXWQrm",
"(V?)PSHUFBrm",
"(V?)PSHUFDmi",
"(V?)PSHUFHWmi",
@@ -1885,12 +1789,6 @@ def: InstRW<[BWWriteResGroup115], (instr
"(V?)PHMINPOSUWrm",
"(V?)PMADDUBSWrm",
"(V?)PMADDWDrm",
- "(V?)PMULDQrm",
- "(V?)PMULHRSWrm",
- "(V?)PMULHUWrm",
- "(V?)PMULHWrm",
- "(V?)PMULLWrm",
- "(V?)PMULUDQrm",
"(V?)PSADBWrm",
"(V?)RCPPSm",
"(V?)RCPSSm",
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=330521&r1=330520&r2=330521&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Sat Apr 21 12:11:55 2018
@@ -679,16 +679,8 @@ def: InstRW<[HWWriteResGroup2], (instreg
"MMX_MOVD64grr",
"(V?)MOVPDI2DIrr",
"(V?)MOVPQIto64rr",
- "(V?)PSLLD(Y?)ri",
- "(V?)PSLLQ(Y?)ri",
"VPSLLVQ(Y?)rr",
- "(V?)PSLLW(Y?)ri",
- "(V?)PSRAD(Y?)ri",
- "(V?)PSRAW(Y?)ri",
- "(V?)PSRLD(Y?)ri",
- "(V?)PSRLQ(Y?)ri",
"VPSRLVQ(Y?)rr",
- "(V?)PSRLW(Y?)ri",
"VTESTPD(Y?)rr",
"VTESTPS(Y?)rr")>;
@@ -717,39 +709,11 @@ def: InstRW<[HWWriteResGroup4], (instreg
"(V?)MOVDI2PDIrr",
"(V?)MOVUPD(Y?)rr",
"(V?)MOVUPS(Y?)rr",
- "(V?)PACKSSDW(Y?)rr",
- "(V?)PACKSSWB(Y?)rr",
- "(V?)PACKUSDW(Y?)rr",
- "(V?)PACKUSWB(Y?)rr",
- "(V?)PALIGNR(Y?)rri",
"(V?)PBLENDW(Y?)rri",
"VPBROADCASTDrr",
"VPBROADCASTQrr",
- "(V?)PMOVSXBDrr",
- "(V?)PMOVSXBQrr",
- "(V?)PMOVSXBWrr",
- "(V?)PMOVSXDQrr",
- "(V?)PMOVSXWDrr",
- "(V?)PMOVSXWQrr",
- "(V?)PMOVZXBDrr",
- "(V?)PMOVZXBQrr",
- "(V?)PMOVZXBWrr",
- "(V?)PMOVZXDQrr",
- "(V?)PMOVZXWDrr",
- "(V?)PMOVZXWQrr",
- "(V?)PSHUFD(Y?)ri",
- "(V?)PSHUFHW(Y?)ri",
- "(V?)PSHUFLW(Y?)ri",
"(V?)PSLLDQ(Y?)ri",
- "(V?)PSRLDQ(Y?)ri",
- "(V?)PUNPCKHBW(Y?)rr",
- "(V?)PUNPCKHDQ(Y?)rr",
- "(V?)PUNPCKHQDQ(Y?)rr",
- "(V?)PUNPCKHWD(Y?)rr",
- "(V?)PUNPCKLBW(Y?)rr",
- "(V?)PUNPCKLDQ(Y?)rr",
- "(V?)PUNPCKLQDQ(Y?)rr",
- "(V?)PUNPCKLWD(Y?)rr")>;
+ "(V?)PSRLDQ(Y?)ri")>;
def HWWriteResGroup5 : SchedWriteRes<[HWPort6]> {
let Latency = 1;
@@ -800,50 +764,7 @@ def: InstRW<[HWWriteResGroup8], (instreg
"BLSI(32|64)rr",
"BLSMSK(32|64)rr",
"BLSR(32|64)rr",
- "LEA(16|32|64)(_32)?r",
- "(V?)PABSB(Y?)rr",
- "(V?)PABSD(Y?)rr",
- "(V?)PABSW(Y?)rr",
- "(V?)PADDB(Y?)rr",
- "(V?)PADDD(Y?)rr",
- "(V?)PADDQ(Y?)rr",
- "(V?)PADDSB(Y?)rr",
- "(V?)PADDSW(Y?)rr",
- "(V?)PADDUSB(Y?)rr",
- "(V?)PADDUSW(Y?)rr",
- "(V?)PADDW(Y?)rr",
- "(V?)PAVGB(Y?)rr",
- "(V?)PAVGW(Y?)rr",
- "(V?)PCMPEQB(Y?)rr",
- "(V?)PCMPEQD(Y?)rr",
- "(V?)PCMPEQQ(Y?)rr",
- "(V?)PCMPEQW(Y?)rr",
- "(V?)PCMPGTB(Y?)rr",
- "(V?)PCMPGTD(Y?)rr",
- "(V?)PCMPGTW(Y?)rr",
- "(V?)PMAXSB(Y?)rr",
- "(V?)PMAXSD(Y?)rr",
- "(V?)PMAXSW(Y?)rr",
- "(V?)PMAXUB(Y?)rr",
- "(V?)PMAXUD(Y?)rr",
- "(V?)PMAXUW(Y?)rr",
- "(V?)PMINSB(Y?)rr",
- "(V?)PMINSD(Y?)rr",
- "(V?)PMINSW(Y?)rr",
- "(V?)PMINUB(Y?)rr",
- "(V?)PMINUD(Y?)rr",
- "(V?)PMINUW(Y?)rr",
- "(V?)PSIGNB(Y?)rr",
- "(V?)PSIGND(Y?)rr",
- "(V?)PSIGNW(Y?)rr",
- "(V?)PSUBB(Y?)rr",
- "(V?)PSUBD(Y?)rr",
- "(V?)PSUBQ(Y?)rr",
- "(V?)PSUBSB(Y?)rr",
- "(V?)PSUBSW(Y?)rr",
- "(V?)PSUBUSB(Y?)rr",
- "(V?)PSUBUSW(Y?)rr",
- "(V?)PSUBW(Y?)rr")>;
+ "LEA(16|32|64)(_32)?r")>;
def HWWriteResGroup9 : SchedWriteRes<[HWPort015]> {
let Latency = 1;
@@ -1061,19 +982,7 @@ def: InstRW<[HWWriteResGroup13_2], (inst
"(V?)PINSRBrm",
"(V?)PINSRDrm",
"(V?)PINSRQrm",
- "(V?)PINSRWrm",
- "(V?)PMOVSXBDrm",
- "(V?)PMOVSXBQrm",
- "(V?)PMOVSXBWrm",
- "(V?)PMOVSXDQrm",
- "(V?)PMOVSXWDrm",
- "(V?)PMOVSXWQrm",
- "(V?)PMOVZXBDrm",
- "(V?)PMOVZXBQrm",
- "(V?)PMOVZXBWrm",
- "(V?)PMOVZXDQrm",
- "(V?)PMOVZXWDrm",
- "(V?)PMOVZXWQrm")>;
+ "(V?)PINSRWrm")>;
def HWWriteResGroup14 : SchedWriteRes<[HWPort6,HWPort23]> {
let Latency = 6;
@@ -2093,16 +2002,7 @@ def HWWriteResGroup89 : SchedWriteRes<[H
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[HWWriteResGroup89], (instregex "(V?)PCMPGTQ(Y?)rr",
- "(V?)PHMINPOSUWrr",
- "(V?)PMADDUBSW(Y?)rr",
- "(V?)PMADDWD(Y?)rr",
- "(V?)PMULDQ(Y?)rr",
- "(V?)PMULHRSW(Y?)rr",
- "(V?)PMULHUW(Y?)rr",
- "(V?)PMULHW(Y?)rr",
- "(V?)PMULLW(Y?)rr",
- "(V?)PMULUDQ(Y?)rr")>;
+def: InstRW<[HWWriteResGroup89], (instregex "(V?)PCMPGTQ(Y?)rr")>;
def HWWriteResGroup90 : SchedWriteRes<[HWPort01]> {
let Latency = 5;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=330521&r1=330520&r2=330521&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Sat Apr 21 12:11:55 2018
@@ -365,39 +365,11 @@ def: InstRW<[SKLWriteResGroup3], (instre
"VBROADCASTSSrr",
"(V?)MOV64toPQIrr",
"(V?)MOVDI2PDIrr",
- "(V?)PACKSSDW(Y?)rr",
- "(V?)PACKSSWB(Y?)rr",
- "(V?)PACKUSDW(Y?)rr",
- "(V?)PACKUSWB(Y?)rr",
- "(V?)PALIGNR(Y?)rri",
"(V?)PBLENDW(Y?)rri",
"VPBROADCASTDrr",
"VPBROADCASTQrr",
- "(V?)PMOVSXBDrr",
- "(V?)PMOVSXBQrr",
- "(V?)PMOVSXBWrr",
- "(V?)PMOVSXDQrr",
- "(V?)PMOVSXWDrr",
- "(V?)PMOVSXWQrr",
- "(V?)PMOVZXBDrr",
- "(V?)PMOVZXBQrr",
- "(V?)PMOVZXBWrr",
- "(V?)PMOVZXDQrr",
- "(V?)PMOVZXWDrr",
- "(V?)PMOVZXWQrr",
- "(V?)PSHUFD(Y?)ri",
- "(V?)PSHUFHW(Y?)ri",
- "(V?)PSHUFLW(Y?)ri",
"(V?)PSLLDQ(Y?)ri",
- "(V?)PSRLDQ(Y?)ri",
- "(V?)PUNPCKHBW(Y?)rr",
- "(V?)PUNPCKHDQ(Y?)rr",
- "(V?)PUNPCKHQDQ(Y?)rr",
- "(V?)PUNPCKHWD(Y?)rr",
- "(V?)PUNPCKLBW(Y?)rr",
- "(V?)PUNPCKLDQ(Y?)rr",
- "(V?)PUNPCKLQDQ(Y?)rr",
- "(V?)PUNPCKLWD(Y?)rr")>;
+ "(V?)PSRLDQ(Y?)ri")>;
def SKLWriteResGroup4 : SchedWriteRes<[SKLPort6]> {
let Latency = 1;
@@ -806,7 +778,7 @@ def: InstRW<[SKLWriteResGroup30], (instr
"VEXTRACTI128rr",
"VINSERTF128rr",
"VINSERTI128rr",
- "VPBROADCASTB(Y?)rr",
+ "VPBROADCASTBrr",
"VPBROADCASTDYrr",
"VPBROADCASTQYrr",
"VPBROADCASTW(Y?)rr",
@@ -1265,19 +1237,7 @@ def: InstRW<[SKLWriteResGroup71], (instr
"(V?)PINSRBrm",
"(V?)PINSRDrm",
"(V?)PINSRQrm",
- "(V?)PINSRWrm",
- "(V?)PMOVSXBDrm",
- "(V?)PMOVSXBQrm",
- "(V?)PMOVSXBWrm",
- "(V?)PMOVSXDQrm",
- "(V?)PMOVSXWDrm",
- "(V?)PMOVSXWQrm",
- "(V?)PMOVZXBDrm",
- "(V?)PMOVZXBQrm",
- "(V?)PMOVZXBWrm",
- "(V?)PMOVZXDQrm",
- "(V?)PMOVZXWDrm",
- "(V?)PMOVZXWQrm")>;
+ "(V?)PINSRWrm")>;
def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,SKLPort23]> {
let Latency = 6;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=330521&r1=330520&r2=330521&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Sat Apr 21 12:11:55 2018
@@ -406,37 +406,9 @@ def: InstRW<[SKXWriteResGroup3], (instre
"MMX_MOVD64to64rr",
"MOV64toPQIrr",
"MOVDI2PDIrr",
- "PACKSSDWrr",
- "PACKSSWBrr",
- "PACKUSDWrr",
- "PACKUSWBrr",
- "PALIGNRrri",
"PBLENDWrri",
- "PMOVSXBDrr",
- "PMOVSXBQrr",
- "PMOVSXBWrr",
- "PMOVSXDQrr",
- "PMOVSXWDrr",
- "PMOVSXWQrr",
- "PMOVZXBDrr",
- "PMOVZXBQrr",
- "PMOVZXBWrr",
- "PMOVZXDQrr",
- "PMOVZXWDrr",
- "PMOVZXWQrr",
- "PSHUFDri",
- "PSHUFHWri",
- "PSHUFLWri",
"PSLLDQri",
"PSRLDQri",
- "PUNPCKHBWrr",
- "PUNPCKHDQrr",
- "PUNPCKHQDQrr",
- "PUNPCKHWDrr",
- "PUNPCKLBWrr",
- "PUNPCKLDQrr",
- "PUNPCKLQDQrr",
- "PUNPCKLWDrr",
"UCOM_FPr",
"UCOM_Fr",
"VBROADCASTI32X2Z128r",
@@ -445,62 +417,10 @@ def: InstRW<[SKXWriteResGroup3], (instre
"VMOV64toPQIrr",
"VMOVDI2PDIZrr",
"VMOVDI2PDIrr",
- "VPACKSSDWYrr",
- "VPACKSSDWZ128rr",
- "VPACKSSDWZ256rr",
- "VPACKSSDWZrr",
- "VPACKSSDWrr",
- "VPACKSSWBYrr",
- "VPACKSSWBZ128rr",
- "VPACKSSWBZ256rr",
- "VPACKSSWBZrr",
- "VPACKSSWBrr",
- "VPACKUSDWYrr",
- "VPACKUSDWZ128rr",
- "VPACKUSDWZ256rr",
- "VPACKUSDWZrr",
- "VPACKUSDWrr",
- "VPACKUSWBYrr",
- "VPACKUSWBZ128rr",
- "VPACKUSWBZ256rr",
- "VPACKUSWBZrr",
- "VPACKUSWBrr",
- "VPALIGNRYrri",
- "VPALIGNRZ128rri",
- "VPALIGNRZ256rri",
- "VPALIGNRZrri",
- "VPALIGNRrri",
"VPBLENDWYrri",
"VPBLENDWrri",
"VPBROADCASTDrr",
"VPBROADCASTQrr",
- "VPMOVSXBDrr",
- "VPMOVSXBQrr",
- "VPMOVSXBWrr",
- "VPMOVSXDQrr",
- "VPMOVSXWDrr",
- "VPMOVSXWQrr",
- "VPMOVZXBDrr",
- "VPMOVZXBQrr",
- "VPMOVZXBWrr",
- "VPMOVZXDQrr",
- "VPMOVZXWDrr",
- "VPMOVZXWQrr",
- "VPSHUFDYri",
- "VPSHUFDZ128ri",
- "VPSHUFDZ256ri",
- "VPSHUFDZri",
- "VPSHUFDri",
- "VPSHUFHWYri",
- "VPSHUFHWZ128ri",
- "VPSHUFHWZ256ri",
- "VPSHUFHWZri",
- "VPSHUFHWri",
- "VPSHUFLWYri",
- "VPSHUFLWZ128ri",
- "VPSHUFLWZ256ri",
- "VPSHUFLWZri",
- "VPSHUFLWri",
"VPSLLDQYri",
"VPSLLDQZ128rr",
"VPSLLDQZ256rr",
@@ -510,47 +430,7 @@ def: InstRW<[SKXWriteResGroup3], (instre
"VPSRLDQZ128rr",
"VPSRLDQZ256rr",
"VPSRLDQZrr",
- "VPSRLDQri",
- "VPUNPCKHBWYrr",
- "VPUNPCKHBWZ128rr",
- "VPUNPCKHBWZ256rr",
- "VPUNPCKHBWZrr",
- "VPUNPCKHBWrr",
- "VPUNPCKHDQYrr",
- "VPUNPCKHDQZ128rr",
- "VPUNPCKHDQZ256rr",
- "VPUNPCKHDQZrr",
- "VPUNPCKHDQrr",
- "VPUNPCKHQDQYrr",
- "VPUNPCKHQDQZ128rr",
- "VPUNPCKHQDQZ256rr",
- "VPUNPCKHQDQZrr",
- "VPUNPCKHQDQrr",
- "VPUNPCKHWDYrr",
- "VPUNPCKHWDZ128rr",
- "VPUNPCKHWDZ256rr",
- "VPUNPCKHWDZrr",
- "VPUNPCKHWDrr",
- "VPUNPCKLBWYrr",
- "VPUNPCKLBWZ128rr",
- "VPUNPCKLBWZ256rr",
- "VPUNPCKLBWZrr",
- "VPUNPCKLBWrr",
- "VPUNPCKLDQYrr",
- "VPUNPCKLDQZ128rr",
- "VPUNPCKLDQZ256rr",
- "VPUNPCKLDQZrr",
- "VPUNPCKLDQrr",
- "VPUNPCKLQDQYrr",
- "VPUNPCKLQDQZ128rr",
- "VPUNPCKLQDQZ256rr",
- "VPUNPCKLQDQZrr",
- "VPUNPCKLQDQrr",
- "VPUNPCKLWDYrr",
- "VPUNPCKLWDZ128rr",
- "VPUNPCKLWDZ256rr",
- "VPUNPCKLWDZrr",
- "VPUNPCKLWDrr")>;
+ "VPSRLDQri")>;
def SKXWriteResGroup4 : SchedWriteRes<[SKXPort6]> {
let Latency = 1;
@@ -2614,18 +2494,6 @@ def: InstRW<[SKXWriteResGroup75], (instr
"PINSRDrm",
"PINSRQrm",
"PINSRWrm",
- "PMOVSXBDrm",
- "PMOVSXBQrm",
- "PMOVSXBWrm",
- "PMOVSXDQrm",
- "PMOVSXWDrm",
- "PMOVSXWQrm",
- "PMOVZXBDrm",
- "PMOVZXBQrm",
- "PMOVZXBWrm",
- "PMOVZXDQrm",
- "PMOVZXWDrm",
- "PMOVZXWQrm",
"VMOVHPDZ128rm(b?)",
"VMOVHPDrm",
"VMOVHPSZ128rm(b?)",
@@ -2641,19 +2509,7 @@ def: InstRW<[SKXWriteResGroup75], (instr
"VPINSRQZrm(b?)",
"VPINSRQrm",
"VPINSRWZrm(b?)",
- "VPINSRWrm",
- "VPMOVSXBDrm",
- "VPMOVSXBQrm",
- "VPMOVSXBWrm",
- "VPMOVSXDQrm",
- "VPMOVSXWDrm",
- "VPMOVSXWQrm",
- "VPMOVZXBDrm",
- "VPMOVZXBQrm",
- "VPMOVZXBWrm",
- "VPMOVZXDQrm",
- "VPMOVZXWDrm",
- "VPMOVZXWQrm")>;
+ "VPINSRWrm")>;
def SKXWriteResGroup76 : SchedWriteRes<[SKXPort6,SKXPort23]> {
let Latency = 6;