[llvm] r330517 - [X86] Add SchedWrites for LDMXCSR/STMXCSR.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Apr 21 11:07:36 PDT 2018
Author: ctopper
Date: Sat Apr 21 11:07:36 2018
New Revision: 330517
URL: http://llvm.org/viewvc/llvm-project?rev=330517&view=rev
Log:
[X86] Add SchedWrites for LDMXCSR/STMXCSR.
Modified:
llvm/trunk/lib/Target/X86/X86InstrSSE.td
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
llvm/trunk/lib/Target/X86/X86Schedule.td
llvm/trunk/lib/Target/X86/X86ScheduleAtom.td
llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
llvm/trunk/lib/Target/X86/X86ScheduleSLM.td
llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=330517&r1=330516&r2=330517&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sat Apr 21 11:07:36 2018
@@ -3117,17 +3117,17 @@ def : Pat<(X86MFence), (MFENCE)>;
def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
"ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>,
- VEX, Sched<[WriteLoad]>, VEX_WIG;
+ VEX, Sched<[WriteLDMXCSR]>, VEX_WIG;
def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
"stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>,
- VEX, Sched<[WriteStore]>, VEX_WIG;
+ VEX, Sched<[WriteSTMXCSR]>, VEX_WIG;
def LDMXCSR : I<0xAE, MRM2m, (outs), (ins i32mem:$src),
"ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>,
- TB, Sched<[WriteLoad]>;
+ TB, Sched<[WriteLDMXCSR]>;
def STMXCSR : I<0xAE, MRM3m, (outs), (ins i32mem:$dst),
"stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>,
- TB, Sched<[WriteStore]>;
+ TB, Sched<[WriteSTMXCSR]>;
//===---------------------------------------------------------------------===//
// SSE2 - Move Aligned/Unaligned Packed Integer Instructions
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=330517&r1=330516&r2=330517&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Sat Apr 21 11:07:36 2018
@@ -303,6 +303,10 @@ def : WriteRes<WriteMicrocoded, [BWPort0
// Fence instructions.
def : WriteRes<WriteFence, [BWPort23, BWPort4]>;
+// Load/store MXCSR.
+def : WriteRes<WriteLDMXCSR, [BWPort0,BWPort23,BWPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
+def : WriteRes<WriteSTMXCSR, [BWPort4,BWPort5,BWPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
+
// Nop, not very useful expect it provides a model for nops!
def : WriteRes<WriteNop, []>;
@@ -673,8 +677,7 @@ def: InstRW<[BWWriteResGroup21], (instre
"(V?)PEXTRBmr",
"(V?)PEXTRDmr",
"(V?)PEXTRQmr",
- "(V?)PEXTRWmr",
- "(V?)STMXCSR")>;
+ "(V?)PEXTRWmr")>;
def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> {
let Latency = 2;
@@ -1535,13 +1538,6 @@ def BWWriteResGroup82 : SchedWriteRes<[B
}
def: InstRW<[BWWriteResGroup82], (instregex "FLDCW16m")>;
-def BWWriteResGroup83 : SchedWriteRes<[BWPort0,BWPort23,BWPort0156]> {
- let Latency = 7;
- let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
-}
-def: InstRW<[BWWriteResGroup83], (instregex "(V?)LDMXCSR")>;
-
def BWWriteResGroup84 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
let Latency = 7;
let NumMicroOps = 3;
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=330517&r1=330516&r2=330517&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Sat Apr 21 11:07:36 2018
@@ -290,6 +290,10 @@ def : WriteRes<WriteCLMulLd, [HWPort0, H
let ResourceCycles = [2,1,1];
}
+// Load/store MXCSR.
+def : WriteRes<WriteLDMXCSR, [HWPort0,HWPort23,HWPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
+def : WriteRes<WriteSTMXCSR, [HWPort4,HWPort5,HWPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
+
def : WriteRes<WriteSystem, [HWPort0156]> { let Latency = 100; }
def : WriteRes<WriteMicrocoded, [HWPort0156]> { let Latency = 100; }
def : WriteRes<WriteFence, [HWPort23, HWPort4]>;
@@ -1269,8 +1273,7 @@ def: InstRW<[HWWriteResGroup20], (instre
"(V?)PEXTRBmr",
"(V?)PEXTRDmr",
"(V?)PEXTRQmr",
- "(V?)PEXTRWmr",
- "(V?)STMXCSR")>;
+ "(V?)PEXTRWmr")>;
def HWWriteResGroup21 : SchedWriteRes<[HWPort4,HWPort6,HWPort237]> {
let Latency = 2;
@@ -1508,13 +1511,6 @@ def HWWriteResGroup39 : SchedWriteRes<[H
}
def: InstRW<[HWWriteResGroup39], (instregex "FLDCW16m")>;
-def HWWriteResGroup40 : SchedWriteRes<[HWPort0,HWPort23,HWPort0156]> {
- let Latency = 7;
- let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
-}
-def: InstRW<[HWWriteResGroup40], (instregex "(V?)LDMXCSR")>;
-
def HWWriteResGroup41 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> {
let Latency = 7;
let NumMicroOps = 3;
Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=330517&r1=330516&r2=330517&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Sat Apr 21 11:07:36 2018
@@ -273,6 +273,10 @@ def : WriteRes<WriteCLMulLd, [SBPort015,
let ResourceCycles = [17, 1];
}
+// Load/store MXCSR.
+// FIXME: This is probably wrong. Only STMXCSR should require Port4.
+def : WriteRes<WriteLDMXCSR, [SBPort0,SBPort4,SBPort5,SBPort23]> { let Latency = 5; let NumMicroOps = 4; let ResourceCycles = [1,1,1,1]; }
+def : WriteRes<WriteSTMXCSR, [SBPort0,SBPort4,SBPort5,SBPort23]> { let Latency = 5; let NumMicroOps = 4; let ResourceCycles = [1,1,1,1]; }
def : WriteRes<WriteSystem, [SBPort015]> { let Latency = 100; }
def : WriteRes<WriteMicrocoded, [SBPort015]> { let Latency = 100; }
@@ -870,14 +874,6 @@ def SBWriteResGroup43 : SchedWriteRes<[S
}
def: InstRW<[SBWriteResGroup43], (instregex "SET(A|BE)m")>;
-def SBWriteResGroup44 : SchedWriteRes<[SBPort0,SBPort4,SBPort5,SBPort23]> {
- let Latency = 5;
- let NumMicroOps = 4;
- let ResourceCycles = [1,1,1,1];
-}
-def: InstRW<[SBWriteResGroup44], (instregex "(V?)LDMXCSR",
- "(V?)STMXCSR")>;
-
def SBWriteResGroup45 : SchedWriteRes<[SBPort0,SBPort4,SBPort23,SBPort15]> {
let Latency = 5;
let NumMicroOps = 4;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=330517&r1=330516&r2=330517&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Sat Apr 21 11:07:36 2018
@@ -309,6 +309,10 @@ def : WriteRes<WriteMicrocoded, [SKLPort
// Fence instructions.
def : WriteRes<WriteFence, [SKLPort23, SKLPort4]>;
+// Load/store MXCSR.
+def : WriteRes<WriteLDMXCSR, [SKLPort0,SKLPort23,SKLPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
+def : WriteRes<WriteSTMXCSR, [SKLPort4,SKLPort5,SKLPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
+
// Nop, not very useful expect it provides a model for nops!
def : WriteRes<WriteNop, []>;
@@ -736,8 +740,7 @@ def: InstRW<[SKLWriteResGroup24], (instr
"(V?)PEXTRBmr",
"(V?)PEXTRDmr",
"(V?)PEXTRQmr",
- "(V?)PEXTRWmr",
- "(V?)STMXCSR")>;
+ "(V?)PEXTRWmr")>;
def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237]> {
let Latency = 2;
@@ -1599,13 +1602,6 @@ def SKLWriteResGroup96 : SchedWriteRes<[
}
def: InstRW<[SKLWriteResGroup96], (instregex "FLDCW16m")>;
-def SKLWriteResGroup97 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort0156]> {
- let Latency = 7;
- let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
-}
-def: InstRW<[SKLWriteResGroup97], (instregex "(V?)LDMXCSR")>;
-
def SKLWriteResGroup98 : SchedWriteRes<[SKLPort6,SKLPort23,SKLPort0156]> {
let Latency = 7;
let NumMicroOps = 3;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=330517&r1=330516&r2=330517&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Sat Apr 21 11:07:36 2018
@@ -309,6 +309,10 @@ def : WriteRes<WriteMicrocoded, [SKXPort
// Fence instructions.
def : WriteRes<WriteFence, [SKXPort23, SKXPort4]>;
+// Load/store MXCSR.
+def : WriteRes<WriteLDMXCSR, [SKXPort0,SKXPort23,SKXPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
+def : WriteRes<WriteSTMXCSR, [SKXPort4,SKXPort5,SKXPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
+
// Nop, not very useful expect it provides a model for nops!
def : WriteRes<WriteNop, []>;
@@ -1371,7 +1375,6 @@ def: InstRW<[SKXWriteResGroup24], (instr
"PEXTRDmr",
"PEXTRQmr",
"PEXTRWmr",
- "STMXCSR",
"VEXTRACTPSZmr(b?)",
"VEXTRACTPSmr",
"VPEXTRBZmr(b?)",
@@ -1381,8 +1384,7 @@ def: InstRW<[SKXWriteResGroup24], (instr
"VPEXTRQZmr(b?)",
"VPEXTRQmr",
"VPEXTRWZmr(b?)",
- "VPEXTRWmr",
- "VSTMXCSR")>;
+ "VPEXTRWmr")>;
def SKXWriteResGroup25 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237]> {
let Latency = 2;
@@ -3248,13 +3250,6 @@ def SKXWriteResGroup101 : SchedWriteRes<
}
def: InstRW<[SKXWriteResGroup101], (instregex "FLDCW16m")>;
-def SKXWriteResGroup102 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort0156]> {
- let Latency = 7;
- let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
-}
-def: InstRW<[SKXWriteResGroup102], (instregex "(V?)LDMXCSR")>;
-
def SKXWriteResGroup103 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort0156]> {
let Latency = 7;
let NumMicroOps = 3;
Modified: llvm/trunk/lib/Target/X86/X86Schedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Schedule.td?rev=330517&r1=330516&r2=330517&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Schedule.td (original)
+++ llvm/trunk/lib/Target/X86/X86Schedule.td Sat Apr 21 11:07:36 2018
@@ -148,6 +148,10 @@ defm WriteAESKeyGen : X86SchedWritePair;
// Carry-less multiplication instructions.
defm WriteCLMul : X86SchedWritePair;
+// Load/store MXCSR
+def WriteLDMXCSR : SchedWrite;
+def WriteSTMXCSR : SchedWrite;
+
// Catch-all for expensive system instructions.
def WriteSystem : SchedWrite;
Modified: llvm/trunk/lib/Target/X86/X86ScheduleAtom.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleAtom.td?rev=330517&r1=330516&r2=330517&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleAtom.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleAtom.td Sat Apr 21 11:07:36 2018
@@ -290,6 +290,13 @@ defm : AtomWriteResPair<WritePHAdd, [Ato
defm : AtomWriteResPair<WriteCLMul, [AtomPort01], [AtomPort01]>; // NOTE: Doesn't exist on Atom.
////////////////////////////////////////////////////////////////////////////////
+// Load/store MXCSR.
+////////////////////////////////////////////////////////////////////////////////
+
+def : WriteRes<WriteLDMXCSR, [AtomPort01]> { let Latency = 5; let ResourceCycles = [5]; }
+def : WriteRes<WriteSTMXCSR, [AtomPort01]> { let Latency = 15; let ResourceCycles = [15]; }
+
+////////////////////////////////////////////////////////////////////////////////
// Special Cases.
////////////////////////////////////////////////////////////////////////////////
@@ -452,7 +459,7 @@ def AtomWrite01_5 : SchedWriteRes<[AtomP
let Latency = 5;
let ResourceCycles = [5];
}
-def : InstRW<[AtomWrite01_5], (instrs FLDCW16m, LDMXCSR,
+def : InstRW<[AtomWrite01_5], (instrs FLDCW16m,
MMX_EMMS)>;
def : InstRW<[AtomWrite01_5], (instregex "ST_FP80m",
"MMX_PH(ADD|SUB)S?Wrr")>;
@@ -558,8 +565,7 @@ def AtomWrite01_15 : SchedWriteRes<[Atom
let Latency = 15;
let ResourceCycles = [15];
}
-def : InstRW<[AtomWrite01_15], (instrs CMPXCHG16rr, CMPXCHG32rr, CMPXCHG64rr,
- STMXCSR)>;
+def : InstRW<[AtomWrite01_15], (instrs CMPXCHG16rr, CMPXCHG32rr, CMPXCHG64rr)>;
def AtomWrite01_17 : SchedWriteRes<[AtomPort01]> {
let Latency = 17;
Modified: llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td?rev=330517&r1=330516&r2=330517&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td Sat Apr 21 11:07:36 2018
@@ -254,6 +254,11 @@ def : WriteRes<WriteLoad, [JLAGU]> { le
def : WriteRes<WriteStore, [JSAGU]>;
def : WriteRes<WriteMove, [JALU01]>;
+// Load/store MXCSR.
+// FIXME: These are copy and pasted from WriteLoad/Store.
+def : WriteRes<WriteLDMXCSR, [JLAGU]> { let Latency = 5; }
+def : WriteRes<WriteSTMXCSR, [JSAGU]>;
+
// Treat misc copies as a move.
def : InstRW<[WriteMove], (instrs COPY)>;
Modified: llvm/trunk/lib/Target/X86/X86ScheduleSLM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleSLM.td?rev=330517&r1=330516&r2=330517&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleSLM.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleSLM.td Sat Apr 21 11:07:36 2018
@@ -84,6 +84,11 @@ def : WriteRes<WriteLoad, [SLM_MEC_RSV]
def : WriteRes<WriteMove, [SLM_IEC_RSV01]>;
def : WriteRes<WriteZero, []>;
+// Load/store MXCSR.
+// FIXME: These are probably wrong. They are copy pasted from WriteStore/Load.
+def : WriteRes<WriteSTMXCSR, [SLM_IEC_RSV01, SLM_MEC_RSV]>;
+def : WriteRes<WriteLDMXCSR, [SLM_MEC_RSV]> { let Latency = 3; }
+
// Treat misc copies as a move.
def : InstRW<[WriteMove], (instrs COPY)>;
Modified: llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td?rev=330517&r1=330516&r2=330517&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td Sat Apr 21 11:07:36 2018
@@ -267,6 +267,8 @@ let Latency = 100 in {
def : WriteRes<WritePCmpEStrMLd, []>;
def : WriteRes<WritePCmpIStrI, []>;
def : WriteRes<WritePCmpIStrILd, []>;
+ def : WriteRes<WriteLDMXCSR, []>;
+ def : WriteRes<WriteSTMXCSR, []>;
}
//=== Regex based InstRW ===//
@@ -1669,10 +1671,4 @@ def : InstRW<[WriteMicrocoded], (instreg
// VZEROALL.
def : InstRW<[WriteMicrocoded], (instregex "VZEROALL")>;
-// LDMXCSR.
-def : InstRW<[WriteMicrocoded], (instregex "(V)?LDMXCSR")>;
-
-// STMXCSR.
-def : InstRW<[WriteMicrocoded], (instregex "(V)?STMXCSR")>;
-
} // SchedModel
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