[llvm] r330505 - [X86][SandyBridge] Strip unnecessary MOVQ/CVT instruction instrw overrides.

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Sat Apr 21 07:03:40 2018
New Revision: 330505

URL: http://llvm.org/viewvc/llvm-project?rev=330505&view=rev
Log:
[X86][SandyBridge] Strip unnecessary MOVQ/CVT instruction instrw overrides.

Modified:
    llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td

Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=330505&r1=330504&r2=330505&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Sat Apr 21 07:03:40 2018
@@ -450,10 +450,8 @@ def SBWriteResGroup6 : SchedWriteRes<[SB
   let ResourceCycles = [1];
 }
 def: InstRW<[SBWriteResGroup6], (instregex "MMX_MOVQ2DQrr",
-                                           "MOVDQArr", //TODO: Why are these separated from their VEX equivalent
-                                           "MOVDQUrr", // TODO: Why are these separated from their VEX equivalent
-                                           "(V?)MOVPQI2QIrr",
-                                           "(V?)MOVZPQILo2PQIrr")>;
+                                           "MOVDQArr", // TODO: Why are these separated from their VEX equivalent
+                                           "MOVDQUrr")>; // TODO: Why are these separated from their VEX equivalent
 
 def SBWriteResGroup7 : SchedWriteRes<[SBPort0]> {
   let Latency = 2;
@@ -589,9 +587,7 @@ def SBWriteResGroup21 : SchedWriteRes<[S
 }
 def: InstRW<[SBWriteResGroup21], (instregex "MMX_CVTPI2PSirr",
                                             "PUSHFS64",
-                                            "(V?)CVTDQ2PS(Y?)rr",
-                                            "(V?)CVTPS2DQ(Y?)rr",
-                                            "(V?)CVTTPS2DQ(Y?)rr")>;
+                                            "(V?)CVTDQ2PS(Y?)rr")>;
 
 def SBWriteResGroup21_16i : SchedWriteRes<[SBPort1, SBPort015]> {
   let Latency = 4;
@@ -1406,8 +1402,6 @@ def: InstRW<[SBWriteResGroup90], (instre
                                             "(V?)ADDSUBPDrm",
                                             "(V?)ADDSUBPSrm",
                                             "(V?)CVTPS2DQrm",
-                                            "(V?)CVTSI642SDrm",
-                                            "(V?)CVTSI2SDrm",
                                             "(V?)CVTTPS2DQrm",
                                             "(V?)ROUNDPDm",
                                             "(V?)ROUNDPSm",