[llvm] r330503 - [X86] Strip unnecessary MMX instruction instrw overrides from scheduler models.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sat Apr 21 05:15:42 PDT 2018
Author: rksimon
Date: Sat Apr 21 05:15:42 2018
New Revision: 330503
URL: http://llvm.org/viewvc/llvm-project?rev=330503&view=rev
Log:
[X86] Strip unnecessary MMX instruction instrw overrides from scheduler models.
Modified:
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
llvm/trunk/lib/Target/X86/X86ScheduleAtom.td
llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=330503&r1=330502&r2=330503&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Sat Apr 21 05:15:42 2018
@@ -322,22 +322,6 @@ def BWWriteResGroup1 : SchedWriteRes<[BW
}
def: InstRW<[BWWriteResGroup1], (instregex "MMX_MOVD64from64rr",
"MMX_MOVD64grr",
- "MMX_PSLLDri",
- "MMX_PSLLDrr",
- "MMX_PSLLQri",
- "MMX_PSLLQrr",
- "MMX_PSLLWri",
- "MMX_PSLLWrr",
- "MMX_PSRADri",
- "MMX_PSRADrr",
- "MMX_PSRAWri",
- "MMX_PSRAWrr",
- "MMX_PSRLDri",
- "MMX_PSRLDrr",
- "MMX_PSRLQri",
- "MMX_PSRLQrr",
- "MMX_PSRLWri",
- "MMX_PSRLWrr",
"(V?)MOVPDI2DIrr",
"(V?)MOVPQIto64rr",
"(V?)PSLLD(Y?)ri",
@@ -371,14 +355,6 @@ def BWWriteResGroup3 : SchedWriteRes<[BW
def: InstRW<[BWWriteResGroup3], (instregex "MMX_MOVD64rr",
"MMX_MOVD64to64rr",
"MMX_MOVQ2DQrr",
- "MMX_PALIGNRrri",
- "MMX_PSHUFWri",
- "MMX_PUNPCKHBWirr",
- "MMX_PUNPCKHDQirr",
- "MMX_PUNPCKHWDirr",
- "MMX_PUNPCKLBWirr",
- "MMX_PUNPCKLDQirr",
- "MMX_PUNPCKLWDirr",
"VBROADCASTSSrr",
"(V?)INSERTPSrr",
"(V?)MOV64toPQIrr",
@@ -482,19 +458,6 @@ def: InstRW<[BWWriteResGroup7], (instreg
"BLSMSK(32|64)rr",
"BLSR(32|64)rr",
"LEA(16|32|64)(_32)?r",
- "MMX_PABS(B|D|W)rr",
- "MMX_PADD(B|D|Q|W)irr",
- "MMX_PADDS(B|W)irr",
- "MMX_PADDUS(B|W)irr",
- "MMX_PAVG(B|W)irr",
- "MMX_PCMPEQ(B|D|W)irr",
- "MMX_PCMPGT(B|D|W)irr",
- "MMX_P(MAX|MIN)SWirr",
- "MMX_P(MAX|MIN)UBirr",
- "MMX_PSIGN(B|D|W)rr",
- "MMX_PSUB(B|D|Q|W)irr",
- "MMX_PSUBS(B|W)irr",
- "MMX_PSUBUS(B|W)irr",
"(V?)PABSB(Y?)rr",
"(V?)PABSD(Y?)rr",
"(V?)PABSW(Y?)rr",
@@ -1012,14 +975,7 @@ def BWWriteResGroup47 : SchedWriteRes<[B
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMADDUBSWrr",
- "MMX_PMADDWDirr",
- "MMX_PMULHRSWrr",
- "MMX_PMULHUWirr",
- "MMX_PMULHWirr",
- "MMX_PMULLWirr",
- "MMX_PMULUDQirr",
- "(V?)PCMPGTQ(Y?)rr",
+def: InstRW<[BWWriteResGroup47], (instregex "(V?)PCMPGTQ(Y?)rr",
"(V?)PHMINPOSUWrr",
"(V?)PMADDUBSW(Y?)rr",
"(V?)PMADDWD(Y?)rr",
@@ -1039,10 +995,7 @@ def BWWriteResGroup49 : SchedWriteRes<[B
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[BWWriteResGroup49], (instregex "MMX_MOVD64rm",
- "MMX_MOVD64to64rm",
- "MMX_MOVQ64rm",
- "MOVSX(16|32|64)rm16",
+def: InstRW<[BWWriteResGroup49], (instregex "MOVSX(16|32|64)rm16",
"MOVSX(16|32|64)rm32",
"MOVSX(16|32|64)rm8",
"MOVZX(16|32|64)rm16",
@@ -1204,7 +1157,6 @@ def BWWriteResGroup61 : SchedWriteRes<[B
def: InstRW<[BWWriteResGroup61], (instregex "MMX_PALIGNRrmi",
"MMX_PINSRWrm",
"MMX_PSHUFBrm",
- "MMX_PSHUFWmi",
"MMX_PUNPCKHBWirm",
"MMX_PUNPCKHDQirm",
"MMX_PUNPCKHWDirm",
@@ -1289,7 +1241,6 @@ def: InstRW<[BWWriteResGroup64], (instre
"BLSI(32|64)rm",
"BLSMSK(32|64)rm",
"BLSR(32|64)rm",
- "MMX_PABS(B|D|W)rm",
"MMX_PADD(B|D|Q|W)irm",
"MMX_PADDS(B|W)irm",
"MMX_PADDUS(B|W)irm",
@@ -1668,8 +1619,6 @@ def BWWriteResGroup91 : SchedWriteRes<[B
let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup91], (instregex "MMX_CVTPI2PSirm",
- "MMX_CVTPS2PIirm",
- "MMX_CVTTPS2PIirm",
"PDEP(32|64)rm",
"PEXT(32|64)rm",
"(V?)ADDPDrm",
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=330503&r1=330502&r2=330503&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Sat Apr 21 05:15:42 2018
@@ -613,10 +613,7 @@ def HWWriteResGroup0_2 : SchedWriteRes<[
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[HWWriteResGroup0_2], (instregex "MMX_MOVD64rm",
- "MMX_MOVD64to64rm",
- "MMX_MOVQ64rm",
- "MOVSX(16|32|64)rm16",
+def: InstRW<[HWWriteResGroup0_2], (instregex "MOVSX(16|32|64)rm16",
"MOVSX(16|32|64)rm32",
"MOVSX(16|32|64)rm8",
"MOVZX(16|32|64)rm16",
@@ -676,22 +673,6 @@ def HWWriteResGroup2 : SchedWriteRes<[HW
}
def: InstRW<[HWWriteResGroup2], (instregex "MMX_MOVD64from64rr",
"MMX_MOVD64grr",
- "MMX_PSLLDri",
- "MMX_PSLLDrr",
- "MMX_PSLLQri",
- "MMX_PSLLQrr",
- "MMX_PSLLWri",
- "MMX_PSLLWrr",
- "MMX_PSRADri",
- "MMX_PSRADrr",
- "MMX_PSRAWri",
- "MMX_PSRAWrr",
- "MMX_PSRLDri",
- "MMX_PSRLDrr",
- "MMX_PSRLQri",
- "MMX_PSRLQrr",
- "MMX_PSRLWri",
- "MMX_PSRLWrr",
"(V?)MOVPDI2DIrr",
"(V?)MOVPQIto64rr",
"(V?)PSLLD(Y?)ri",
@@ -725,14 +706,6 @@ def HWWriteResGroup4 : SchedWriteRes<[HW
def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVD64rr",
"MMX_MOVD64to64rr",
"MMX_MOVQ2DQrr",
- "MMX_PALIGNRrri",
- "MMX_PSHUFWri",
- "MMX_PUNPCKHBWirr",
- "MMX_PUNPCKHDQirr",
- "MMX_PUNPCKHWDirr",
- "MMX_PUNPCKLBWirr",
- "MMX_PUNPCKLDQirr",
- "MMX_PUNPCKLWDirr",
"VBROADCASTSSrr",
"(V?)INSERTPSrr",
"(V?)MOV64toPQIrr",
@@ -840,19 +813,6 @@ def: InstRW<[HWWriteResGroup8], (instreg
"BLSMSK(32|64)rr",
"BLSR(32|64)rr",
"LEA(16|32|64)(_32)?r",
- "MMX_PABS(B|D|W)rr",
- "MMX_PADD(B|D|Q|W)irr",
- "MMX_PADDS(B|W)irr",
- "MMX_PADDUS(B|W)irr",
- "MMX_PAVG(B|W)irr",
- "MMX_PCMPEQ(B|D|W)irr",
- "MMX_PCMPGT(B|D|W)irr",
- "MMX_P(MAX|MIN)SWirr",
- "MMX_P(MAX|MIN)UBirr",
- "MMX_PSIGN(B|D|W)rr",
- "MMX_PSUB(B|D|Q|W)irr",
- "MMX_PSUBS(B|W)irr",
- "MMX_PSUBUS(B|W)irr",
"(V?)PABSB(Y?)rr",
"(V?)PABSD(Y?)rr",
"(V?)PABSW(Y?)rr",
@@ -903,10 +863,6 @@ def HWWriteResGroup9 : SchedWriteRes<[HW
let ResourceCycles = [1];
}
def: InstRW<[HWWriteResGroup9], (instregex "MMX_MOVQ64rr",
- "MMX_PANDNirr",
- "MMX_PANDirr",
- "MMX_PORirr",
- "MMX_PXORirr",
"(V?)BLENDPD(Y?)rri",
"(V?)BLENDPS(Y?)rri",
"(V?)MOVDQA(Y?)rr",
@@ -990,8 +946,6 @@ def: InstRW<[HWWriteResGroup12], (instre
"FCOMP32m",
"FCOMP64m",
"MMX_CVTPI2PSirm",
- "MMX_CVTPS2PIirm",
- "MMX_CVTTPS2PIirm",
"PDEP(32|64)rm",
"PEXT(32|64)rm",
"(V?)ADDSDrm",
@@ -1108,7 +1062,6 @@ def HWWriteResGroup13_2 : SchedWriteRes<
def: InstRW<[HWWriteResGroup13_2], (instregex "MMX_PALIGNRrmi",
"MMX_PINSRWrm",
"MMX_PSHUFBrm",
- "MMX_PSHUFWmi",
"MMX_PUNPCKHBWirm",
"MMX_PUNPCKHDQirm",
"MMX_PUNPCKHWDirm",
@@ -1164,7 +1117,6 @@ def: InstRW<[HWWriteResGroup16], (instre
"BLSI(32|64)rm",
"BLSMSK(32|64)rm",
"BLSR(32|64)rm",
- "MMX_PABS(B|D|W)rm",
"MMX_PADD(B|D|Q|W)irm",
"MMX_PADDS(B|W)irm",
"MMX_PADDUS(B|W)irm",
@@ -2173,14 +2125,7 @@ def HWWriteResGroup89 : SchedWriteRes<[H
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[HWWriteResGroup89], (instregex "MMX_PMADDUBSWrr",
- "MMX_PMADDWDirr",
- "MMX_PMULHRSWrr",
- "MMX_PMULHUWirr",
- "MMX_PMULHWirr",
- "MMX_PMULLWirr",
- "MMX_PMULUDQirr",
- "(V?)PCMPGTQ(Y?)rr",
+def: InstRW<[HWWriteResGroup89], (instregex "(V?)PCMPGTQ(Y?)rr",
"(V?)PHMINPOSUWrr",
"(V?)PMADDUBSW(Y?)rr",
"(V?)PMADDWD(Y?)rr",
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=330503&r1=330502&r2=330503&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Sat Apr 21 05:15:42 2018
@@ -342,22 +342,6 @@ def: InstRW<[SKLWriteResGroup1], (instre
"MMX_PMAXUBirr",
"MMX_PMINSWirr",
"MMX_PMINUBirr",
- "MMX_PSLLDri",
- "MMX_PSLLDrr",
- "MMX_PSLLQri",
- "MMX_PSLLQrr",
- "MMX_PSLLWri",
- "MMX_PSLLWrr",
- "MMX_PSRADri",
- "MMX_PSRADrr",
- "MMX_PSRAWri",
- "MMX_PSRAWrr",
- "MMX_PSRLDri",
- "MMX_PSRLDrr",
- "MMX_PSRLQri",
- "MMX_PSRLQrr",
- "MMX_PSRLWri",
- "MMX_PSRLWrr",
"MMX_PSUBSBirr",
"MMX_PSUBSWirr",
"MMX_PSUBUSBirr",
@@ -372,14 +356,6 @@ def: InstRW<[SKLWriteResGroup3], (instre
"COM_FST0r",
"MMX_MOVD64rr",
"MMX_MOVD64to64rr",
- "MMX_PALIGNRrri",
- "MMX_PSHUFWri",
- "MMX_PUNPCKHBWirr",
- "MMX_PUNPCKHDQirr",
- "MMX_PUNPCKHWDirr",
- "MMX_PUNPCKLBWirr",
- "MMX_PUNPCKLDQirr",
- "MMX_PUNPCKLWDirr",
"UCOM_FPr",
"UCOM_Fr",
"VBROADCASTSSrr",
@@ -1134,10 +1110,7 @@ def SKLWriteResGroup58 : SchedWriteRes<[
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup58], (instregex "MMX_MOVD64rm",
- "MMX_MOVD64to64rm",
- "MMX_MOVQ64rm",
- "MOVSX(16|32|64)rm16",
+def: InstRW<[SKLWriteResGroup58], (instregex "MOVSX(16|32|64)rm16",
"MOVSX(16|32|64)rm32",
"MOVSX(16|32|64)rm8",
"MOVZX(16|32|64)rm16",
@@ -1298,7 +1271,6 @@ def SKLWriteResGroup71 : SchedWriteRes<[
def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PALIGNRrmi",
"MMX_PINSRWrm",
"MMX_PSHUFBrm",
- "MMX_PSHUFWmi",
"MMX_PUNPCKHBWirm",
"MMX_PUNPCKHDQirm",
"MMX_PUNPCKHWDirm",
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=330503&r1=330502&r2=330503&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Sat Apr 21 05:15:42 2018
@@ -370,22 +370,6 @@ def: InstRW<[SKXWriteResGroup1], (instre
"MMX_PMAXUBirr",
"MMX_PMINSWirr",
"MMX_PMINUBirr",
- "MMX_PSLLDri",
- "MMX_PSLLDrr",
- "MMX_PSLLQri",
- "MMX_PSLLQrr",
- "MMX_PSLLWri",
- "MMX_PSLLWrr",
- "MMX_PSRADri",
- "MMX_PSRADrr",
- "MMX_PSRAWri",
- "MMX_PSRAWrr",
- "MMX_PSRLDri",
- "MMX_PSRLDrr",
- "MMX_PSRLQri",
- "MMX_PSRLQrr",
- "MMX_PSRLWri",
- "MMX_PSRLWrr",
"MMX_PSUBSBirr",
"MMX_PSUBSWirr",
"MMX_PSUBUSBirr",
@@ -416,14 +400,6 @@ def: InstRW<[SKXWriteResGroup3], (instre
"KMOVWkr",
"MMX_MOVD64rr",
"MMX_MOVD64to64rr",
- "MMX_PALIGNRrri",
- "MMX_PSHUFWri",
- "MMX_PUNPCKHBWirr",
- "MMX_PUNPCKHDQirr",
- "MMX_PUNPCKHWDirr",
- "MMX_PUNPCKLBWirr",
- "MMX_PUNPCKLDQirr",
- "MMX_PUNPCKLWDirr",
"MOV64toPQIrr",
"MOVDDUPrr",
"MOVDI2PDIrr",
@@ -2405,10 +2381,7 @@ def SKXWriteResGroup58 : SchedWriteRes<[
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKXWriteResGroup58], (instregex "MMX_MOVD64rm",
- "MMX_MOVD64to64rm",
- "MMX_MOVQ64rm",
- "MOV64toPQIrm",
+def: InstRW<[SKXWriteResGroup58], (instregex "MOV64toPQIrm",
"MOVDDUPrm",
"MOVDI2PDIrm",
"MOVQI2PQIrm",
@@ -2730,7 +2703,6 @@ def SKXWriteResGroup75 : SchedWriteRes<[
def: InstRW<[SKXWriteResGroup75], (instregex "MMX_PALIGNRrmi",
"MMX_PINSRWrm",
"MMX_PSHUFBrm",
- "MMX_PSHUFWmi",
"MMX_PUNPCKHBWirm",
"MMX_PUNPCKHDQirm",
"MMX_PUNPCKHWDirm",
Modified: llvm/trunk/lib/Target/X86/X86ScheduleAtom.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleAtom.td?rev=330503&r1=330502&r2=330503&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleAtom.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleAtom.td Sat Apr 21 05:15:42 2018
@@ -303,8 +303,8 @@ def : InstRW<[AtomWrite0_1], (instrs FXA
DEC8m, DEC16m, DEC32m, DEC64m,
INC8m, INC16m, INC32m, INC64m,
MOVSX64rr32,
- MMX_MOVD64rr, MMX_MOVD64mr,
- MMX_MOVD64to64rr, MMX_MOVD64to64rm,
+ MMX_MOVD64rr,
+ MMX_MOVD64to64rr,
MMX_PSHUFBrr, MMX_PSHUFBrm,
MOVDI2PDIrr, MOVDI2PDIrm,
MOV64toPQIrr, MOV64toPQIrm,
@@ -315,11 +315,10 @@ def : InstRW<[AtomWrite0_1], (instregex
"(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
"MOV(S|Z)X(32|64)(rr|rm)(8|8_NOREX|16)",
"LD_F(P)?(16|32|64)?(m|rr)",
- "MMX_MASKMOVQ(64)?",
"MMX_PAVG(B|W)irm",
"MMX_P(MAX|MIN)(UB|SW)irm",
"MMX_PSIGN(B|D|W)rm")>;
-
+
def AtomWrite0_3 : SchedWriteRes<[AtomPort0]> {
let Latency = 3;
let ResourceCycles = [3];
@@ -396,9 +395,6 @@ def : InstRW<[AtomWrite01_1], (instrs FD
MOVSSrr, MOVSSrr_REV,
PSLLDQri, PSRLDQri)>;
def : InstRW<[AtomWrite01_1], (instregex "(MMX_)?PS(LL|RA|RL)(D|Q|W)ri",
- "MMX_PAVG(B|W)irr",
- "MMX_P(MAX|MIN)(UB|SW)irr",
- "MMX_PSIGN(B|D|W)rr",
"MMX_PACK(SSDW|SSWB|USWB)irr",
"MMX_PUNPCKH(BW|DQ|WD)irr")>;
Modified: llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td?rev=330503&r1=330502&r2=330503&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td Sat Apr 21 05:15:42 2018
@@ -900,12 +900,6 @@ def : InstRW<[ZnWriteFPU], (instregex "M
// y <- y.
def : InstRW<[ZnWriteFPUY], (instregex "VMOVDQ(A|U)Yrr")>;
-// MOVDQ2Q.
-def : InstRW<[ZnWriteFPU], (instregex "MMX_MOVDQ2Qrr")>;
-
-// MOVQ2DQ.
-def : InstRW<[ZnWriteFPU], (instregex "MMX_MOVQ2DQrr")>;
-
// PACKSSWB/DW.
// mm <- mm.
def ZnWriteFPU12 : SchedWriteRes<[ZnFPU12]> ;
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