[llvm] r330465 - [X86][SandyBridge] Remove duplciate InstRWs from Sandy Brige scheduler model.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 20 11:55:40 PDT 2018
Author: ctopper
Date: Fri Apr 20 11:55:40 2018
New Revision: 330465
URL: http://llvm.org/viewvc/llvm-project?rev=330465&view=rev
Log:
[X86][SandyBridge] Remove duplciate InstRWs from Sandy Brige scheduler model.
Modified:
llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=330465&r1=330464&r2=330465&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Fri Apr 20 11:55:40 2018
@@ -330,24 +330,8 @@ def: InstRW<[SBWriteResGroup2], (instreg
"ST_FPrr",
"ST_Frr",
"VEXTRACTF128rr",
- "VINSERTF128rr",
- "(V?)INSERTPSrr",
"(V?)MOV64toPQIrr",
- "(V?)MOVDDUP(Y?)rr",
- "(V?)MOVDI2PDIrr",
- "(V?)MOVHLPSrr",
- "(V?)MOVLHPSrr",
- "(V?)MOVSDrr",
- "(V?)MOVSHDUP(Y?)rr",
- "(V?)MOVSLDUP(Y?)rr",
- "(V?)MOVSSrr",
- "(V?)MOVUPD(Y?)rr",
- "(V?)MOVUPS(Y?)rr",
- "VPERM2F128rr",
- "VPERMILPD(Y?)ri",
- "VPERMILPS(Y?)ri",
- "(V?)SHUFPD(Y?)rri",
- "(V?)SHUFPS(Y?)rri")>;
+ "(V?)MOVDI2PDIrr")>;
def SBWriteResGroup3 : SchedWriteRes<[SBPort01]> {
let Latency = 1;
@@ -463,8 +447,7 @@ def SBWriteResGroup6 : SchedWriteRes<[SB
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SBWriteResGroup6], (instregex "MMX_MOVD64from64rr",
- "MMX_MOVQ2DQrr",
+def: InstRW<[SBWriteResGroup6], (instregex "MMX_MOVQ2DQrr",
"MOVDQArr", //TODO: Why are these separated from their VEX equivalent
"MOVDQUrr", // TODO: Why are these separated from their VEX equivalent
"(V?)MOVPQI2QIrr",
@@ -601,19 +584,6 @@ def: InstRW<[SBWriteResGroup19], (instre
"SHLD(16|32|64)rri8",
"SHRD(16|32|64)rri8")>;
-def SBWriteResGroup20 : SchedWriteRes<[SBPort0]> {
- let Latency = 5;
- let NumMicroOps = 1;
- let ResourceCycles = [1];
-}
-def: InstRW<[SBWriteResGroup20], (instregex "MMX_PMADDUBSWrr",
- "MMX_PMADDWDirr",
- "MMX_PMULHRSWrr",
- "MMX_PMULHUWirr",
- "MMX_PMULHWirr",
- "MMX_PMULLWirr",
- "MMX_PMULUDQirr")>;
-
def SBWriteResGroup21 : SchedWriteRes<[SBPort1]> {
let Latency = 3;
let NumMicroOps = 1;
@@ -623,8 +593,6 @@ def: InstRW<[SBWriteResGroup21], (instre
"ADD_FST0r",
"ADD_FrST0",
"MMX_CVTPI2PSirr",
- "MMX_CVTPS2PIirr",
- "MMX_CVTTPS2PIirr",
"PUSHFS64",
"SUBR_FPrST0",
"SUBR_FST0r",
@@ -634,11 +602,7 @@ def: InstRW<[SBWriteResGroup21], (instre
"SUB_FrST0",
"(V?)CVTDQ2PS(Y?)rr",
"(V?)CVTPS2DQ(Y?)rr",
- "(V?)CVTTPS2DQ(Y?)rr",
- "(V?)ROUNDPD(Y?)r",
- "(V?)ROUNDPS(Y?)r",
- "(V?)ROUNDSDr",
- "(V?)ROUNDSSr")>;
+ "(V?)CVTTPS2DQ(Y?)rr")>;
def SBWriteResGroup21_16i : SchedWriteRes<[SBPort1, SBPort015]> {
let Latency = 4;
@@ -802,16 +766,7 @@ def SBWriteResGroup30 : SchedWriteRes<[S
def: InstRW<[SBWriteResGroup30], (instregex "MUL_FPrST0",
"MUL_FST0r",
"MUL_FrST0",
- "(V?)MULPD(Y?)rr",
- "(V?)MULPS(Y?)rr",
- "(V?)MULSDrr",
- "(V?)MULSSrr",
- "(V?)PCMPGTQrr",
- "(V?)PHMINPOSUWrr",
- "(V?)RCPPSr",
- "(V?)RCPSSr",
- "(V?)RSQRTPSr",
- "(V?)RSQRTSSr")>;
+ "(V?)PCMPGTQrr")>;
def SBWriteResGroup31 : SchedWriteRes<[SBPort23]> {
let Latency = 5;
@@ -822,8 +777,7 @@ def: InstRW<[SBWriteResGroup31], (instre
"MOVSX(16|32|64)rm32",
"MOVSX(16|32|64)rm8",
"MOVZX(16|32|64)rm16",
- "MOVZX(16|32|64)rm8",
- "PREFETCH")>;
+ "MOVZX(16|32|64)rm8")>;
def SBWriteResGroup32 : SchedWriteRes<[SBPort0,SBPort1]> {
let Latency = 5;
@@ -974,11 +928,9 @@ def SBWriteResGroup48 : SchedWriteRes<[S
def: InstRW<[SBWriteResGroup48], (instregex "MMX_MOVD64from64rm",
"POP(16|32|64)r",
"VBROADCASTSSrm",
- "(V?)LDDQU(Y?)rm",
"(V?)MOV64toPQIrm",
"(V?)MOVDDUPrm",
"(V?)MOVDI2PDIrm",
- "(V?)MOVNTDQArm",
"(V?)MOVQI2PQIrm",
"(V?)MOVSDrm",
"(V?)MOVSHDUPrm",
@@ -1278,10 +1230,6 @@ def SBWriteResGroup72 : SchedWriteRes<[S
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SBWriteResGroup72], (instregex "FCOM32m",
- "FCOM64m",
- "FCOMP32m",
- "FCOMP64m")>;
def: InstRW<[SBWriteResGroup72], (instrs MUL8m)>;
def SBWriteResGroup73 : SchedWriteRes<[SBPort5,SBPort23]> {
@@ -1476,8 +1424,7 @@ def SBWriteResGroup90 : SchedWriteRes<[S
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SBWriteResGroup90], (instregex "MMX_CVTPI2PSirm",
- "MMX_CVTPS2PIirm",
+def: InstRW<[SBWriteResGroup90], (instregex "MMX_CVTPS2PIirm",
"MMX_CVTTPS2PIirm",
"POPCNT(16|32|64)rm",
"(V?)ADDPDrm",
@@ -1486,7 +1433,6 @@ def: InstRW<[SBWriteResGroup90], (instre
"(V?)ADDSSrm",
"(V?)ADDSUBPDrm",
"(V?)ADDSUBPSrm",
- "(V?)CVTDQ2PSrm",
"(V?)CVTPS2DQrm",
"(V?)CVTSI642SDrm",
"(V?)CVTSI2SDrm",
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