[llvm] r330396 - [Sparc] Use synthetic instruction clr to zero register instead of sethi
Daniel Cederman via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 20 00:47:12 PDT 2018
Author: dcederman
Date: Fri Apr 20 00:47:12 2018
New Revision: 330396
URL: http://llvm.org/viewvc/llvm-project?rev=330396&view=rev
Log:
[Sparc] Use synthetic instruction clr to zero register instead of sethi
Using `clr reg`/`mov %g0, reg`/`or %g0, %g0, reg` to zero a register
looks much better than `sethi 0, reg`.
Reviewers: jyknight, venkatra
Reviewed By: jyknight
Subscribers: eraman, fedor.sergeev, jrtc27, llvm-commits
Differential Revision: https://reviews.llvm.org/D45810
Added:
llvm/trunk/test/CodeGen/SPARC/imm.ll
Modified:
llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td
llvm/trunk/test/CodeGen/SPARC/atomics.ll
llvm/trunk/test/CodeGen/SPARC/inlineasm.ll
llvm/trunk/test/CodeGen/SPARC/vector-extract-elt.ll
Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td?rev=330396&r1=330395&r2=330396&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td Fri Apr 20 00:47:12 2018
@@ -1599,6 +1599,9 @@ let Predicates = [HasV9] in {
// Non-Instruction Patterns
//===----------------------------------------------------------------------===//
+// Zero immediate.
+def : Pat<(i32 0),
+ (ORrr (i32 G0), (i32 G0))>;
// Small immediates.
def : Pat<(i32 simm13:$val),
(ORri (i32 G0), imm:$val)>;
Modified: llvm/trunk/test/CodeGen/SPARC/atomics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/atomics.ll?rev=330396&r1=330395&r2=330396&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SPARC/atomics.ll (original)
+++ llvm/trunk/test/CodeGen/SPARC/atomics.ll Fri Apr 20 00:47:12 2018
@@ -82,7 +82,7 @@ entry:
; CHECK: and %o0, 255, %o0
; CHECK: sll %o0, %o1, %o0
; CHECK: andn %g2, %o5, %g2
-; CHECK: sethi 0, %o5
+; CHECK: mov %g0, %o5
; CHECK: [[LABEL1:\.L.*]]:
; CHECK: or %g2, %o4, %g3
; CHECK: or %g2, %o0, %g4
@@ -123,7 +123,7 @@ entry:
; CHECK: sll %o0, %o1, %o0
; CHECK: sll %o4, %o1, %o4
; CHECK: andn %g2, %o5, %g2
-; CHECK: sethi 0, %o5
+; CHECK: mov %g0, %o5
; CHECK: [[LABEL1:\.L.*]]:
; CHECK: or %g2, %o0, %g3
; CHECK: or %g2, %o4, %g4
@@ -235,6 +235,7 @@ entry:
; CHECK-LABEL: test_load_add_i32
; CHECK: membar
+; CHECK: mov %g0
; CHECK: mov [[U:%[gilo][0-7]]], [[V:%[gilo][0-7]]]
; CHECK: add [[U:%[gilo][0-7]]], %o1, [[V2:%[gilo][0-7]]]
; CHECK: cas [%o0], [[V]], [[V2]]
Added: llvm/trunk/test/CodeGen/SPARC/imm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/imm.ll?rev=330396&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/SPARC/imm.ll (added)
+++ llvm/trunk/test/CodeGen/SPARC/imm.ll Fri Apr 20 00:47:12 2018
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=sparc | FileCheck %s -check-prefix=SPARC
+
+; Materializing constants
+
+define i32 @zero() nounwind {
+; SPARC-LABEL: zero:
+; SPARC: ! %bb.0:
+; SPARC-NEXT: retl
+; SPARC-NEXT: mov %g0, %o0
+ret i32 0
+}
+
+define i32 @pos_small() nounwind {
+; SPARC-LABEL: pos_small:
+; SPARC: ! %bb.0:
+; SPARC-NEXT: retl
+; SPARC-NEXT: mov 2047, %o0
+ ret i32 2047
+}
+
+define i32 @neg_small() nounwind {
+; SPARC-LABEL: neg_small:
+; SPARC: ! %bb.0:
+; SPARC-NEXT: retl
+; SPARC-NEXT: mov -2047, %o0
+ ret i32 -2047
+}
+
+define i32 @pos_i32() nounwind {
+; SPARC-LABEL: pos_i32:
+; SPARC: ! %bb.0:
+; SPARC-NEXT: sethi 1695242, %o0
+; SPARC-NEXT: retl
+; SPARC-NEXT: or %o0, 751, %o0
+ ret i32 1735928559
+}
+
+define i32 @neg_i32() nounwind {
+; SPARC-LABEL: neg_i32:
+; SPARC: ! %bb.0:
+; SPARC-NEXT: sethi 3648367, %o0
+; SPARC-NEXT: retl
+; SPARC-NEXT: or %o0, 751, %o0
+ ret i32 -559038737
+}
Modified: llvm/trunk/test/CodeGen/SPARC/inlineasm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/inlineasm.ll?rev=330396&r1=330395&r2=330396&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SPARC/inlineasm.ll (original)
+++ llvm/trunk/test/CodeGen/SPARC/inlineasm.ll Fri Apr 20 00:47:12 2018
@@ -84,7 +84,7 @@ attributes #0 = { "no-frame-pointer-elim
;; Ensures that tied in and out gets allocated properly.
; CHECK-LABEL: test_i64_inout:
-; CHECK: sethi 0, %o2
+; CHECK: mov %g0, %o2
; CHECK: mov 5, %o3
; CHECK: xor %o2, %g0, %o2
; CHECK: mov %o2, %o0
Modified: llvm/trunk/test/CodeGen/SPARC/vector-extract-elt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/vector-extract-elt.ll?rev=330396&r1=330395&r2=330396&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SPARC/vector-extract-elt.ll (original)
+++ llvm/trunk/test/CodeGen/SPARC/vector-extract-elt.ll Fri Apr 20 00:47:12 2018
@@ -7,7 +7,7 @@
define i1 @test1(<4 x i16>* %in) {
; CHECK-LABEL: ! %bb.0:
; CHECK-NEXT: retl
-; CHECK-NEXT: sethi 0, %o0
+; CHECK-NEXT: mov %g0, %o0
%vec2 = load <4 x i16>, <4 x i16>* %in, align 1
%vec3 = lshr <4 x i16> %vec2, <i16 2, i16 2, i16 2, i16 2>
%vec4 = sext <4 x i16> %vec3 to <4 x i32>
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