[llvm] r330273 - [Power9]Legalize and emit code for converting (Un)Signed Word to Quad-Precision
Lei Huang via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 18 09:34:22 PDT 2018
Author: lei
Date: Wed Apr 18 09:34:22 2018
New Revision: 330273
URL: http://llvm.org/viewvc/llvm-project?rev=330273&view=rev
Log:
[Power9]Legalize and emit code for converting (Un)Signed Word to Quad-Precision
Legalize and emit code for converting (Un)Signed Word to quad-precision via:
xscvsdqp
xscvudqp
Differential Revision: https://reviews.llvm.org/D45389
Modified:
llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td
llvm/trunk/test/CodeGen/PowerPC/f128-conv.ll
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td?rev=330273&r1=330272&r2=330273&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td Wed Apr 18 09:34:22 2018
@@ -2514,11 +2514,20 @@ let AddedComplexity = 400, Predicates =
def XSCVSDQP : X_VT5_XO5_VB5_TyVB<63, 10, 836, "xscvsdqp", vfrc, []>;
def : Pat<(f128 (sint_to_fp i64:$src)),
(f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>;
-
def XSCVUDQP : X_VT5_XO5_VB5_TyVB<63, 2, 836, "xscvudqp", vfrc, []>;
def : Pat<(f128 (uint_to_fp i64:$src)),
(f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>;
+ // Convert (Un)Signed Word -> QP
+ def : Pat<(f128 (sint_to_fp i32:$src)),
+ (f128 (XSCVSDQP (MTVSRWA $src)))>;
+ def : Pat<(f128 (sint_to_fp (i32 (load xoaddr:$src)))),
+ (f128 (XSCVSDQP (LIWAX xoaddr:$src)))>;
+ def : Pat<(f128 (uint_to_fp i32:$src)),
+ (f128 (XSCVUDQP (MTVSRWZ $src)))>;
+ def : Pat<(f128 (uint_to_fp (i32 (load xoaddr:$src)))),
+ (f128 (XSCVUDQP (LIWZX xoaddr:$src)))>;
+
let UseVSXReg = 1 in {
//===--------------------------------------------------------------------===//
// Round to Floating-Point Integer Instructions
Modified: llvm/trunk/test/CodeGen/PowerPC/f128-conv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/f128-conv.ll?rev=330273&r1=330272&r2=330273&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/f128-conv.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/f128-conv.ll Wed Apr 18 09:34:22 2018
@@ -1,9 +1,11 @@
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
-; RUN: -enable-ppc-quad-precision -ppc-vsr-nums-as-vr < %s | FileCheck %s
+; RUN: -enable-ppc-quad-precision -ppc-vsr-nums-as-vr \
+; RUN: -verify-machineinstrs < %s | FileCheck %s
@mem = global [5 x i64] [i64 56, i64 63, i64 3, i64 5, i64 6], align 8
@umem = global [5 x i64] [i64 560, i64 100, i64 34, i64 2, i64 5], align 8
@swMem = global [5 x i32] [i32 5, i32 2, i32 3, i32 4, i32 0], align 4
+ at uwMem = global [5 x i32] [i32 5, i32 2, i32 3, i32 4, i32 0], align 4
; Function Attrs: norecurse nounwind
define void @sdwConv2qp(fp128* nocapture %a, i64 %b) {
@@ -137,4 +139,161 @@ entry:
; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG1]]
; CHECK-NEXT: stxv [[CONV]], 0(3)
; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @swConv2qp(fp128* nocapture %a, i32 signext %b) {
+entry:
+ %conv = sitofp i32 %b to fp128
+ store fp128 %conv, fp128* %a, align 16
+ ret void
+
+; CHECK-LABEL: swConv2qp
+; CHECK-NOT: lwz
+; CHECK: mtvsrwa [[REG0:[0-9]+]], 4
+; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG1]]
+; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @swConv2qp_02(fp128* nocapture %a, i32* nocapture readonly %b) {
+entry:
+ %0 = load i32, i32* %b, align 4
+ %conv = sitofp i32 %0 to fp128
+ store fp128 %conv, fp128* %a, align 16
+ ret void
+
+; CHECK-LABEL: swConv2qp_02
+; CHECK-NOT: lwz
+; CHECK: lxsiwax [[REG:[0-9]+]], 0, 4
+; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG]]
+; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @swConv2qp_03(fp128* nocapture %a) {
+entry:
+ %0 = load i32, i32* getelementptr inbounds
+ ([5 x i32], [5 x i32]* @swMem, i64 0, i64 3), align 4
+ %conv = sitofp i32 %0 to fp128
+ store fp128 %conv, fp128* %a, align 16
+ ret void
+
+; CHECK-LABEL: swConv2qp_03
+; CHECK: addis [[REG:[0-9]+]], 2, .LC2 at toc@ha
+; CHECK: ld [[REG]], .LC2 at toc@l([[REG]])
+; CHECK: addi [[REG2:[0-9]+]], [[REG]], 12
+; CHECK: lxsiwax [[REG0:[0-9]+]], 0, [[REG2]]
+; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG0]]
+; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @uwConv2qp(fp128* nocapture %a, i32 zeroext %b) {
+entry:
+ %conv = uitofp i32 %b to fp128
+ store fp128 %conv, fp128* %a, align 16
+ ret void
+
+; CHECK-LABEL: uwConv2qp
+; CHECK-NOT: lwz
+; CHECK: mtvsrwz [[REG:[0-9]+]], 4
+; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
+; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @uwConv2qp_02(fp128* nocapture %a, i32* nocapture readonly %b) {
+entry:
+ %0 = load i32, i32* %b, align 4
+ %conv = uitofp i32 %0 to fp128
+ store fp128 %conv, fp128* %a, align 16
+ ret void
+
+; CHECK-LABEL: uwConv2qp_02
+; CHECK-NOT: lwz
+; CHECK: lxsiwzx [[REG:[0-9]+]], 0, 4
+; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
+; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @uwConv2qp_03(fp128* nocapture %a) {
+entry:
+ %0 = load i32, i32* getelementptr inbounds
+ ([5 x i32], [5 x i32]* @uwMem, i64 0, i64 3), align 4
+ %conv = uitofp i32 %0 to fp128
+ store fp128 %conv, fp128* %a, align 16
+ ret void
+
+; CHECK-LABEL: uwConv2qp_03
+; CHECK: addis [[REG:[0-9]+]], 2, .LC3 at toc@ha
+; CHECK-NEXT: ld [[REG]], .LC3 at toc@l([[REG]])
+; CHECK-NEXT: addi [[REG2:[0-9]+]], [[REG]], 12
+; CHECK-NEXT: lxsiwzx [[REG1:[0-9]+]], 0, [[REG2]]
+; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG1]]
+; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @uwConv2qp_04(fp128* nocapture %a,
+ i32 zeroext %b, i32* nocapture readonly %c) {
+entry:
+ %0 = load i32, i32* %c, align 4
+ %add = add i32 %0, %b
+ %conv = uitofp i32 %add to fp128
+ store fp128 %conv, fp128* %a, align 16
+ ret void
+
+; CHECK-LABEL: uwConv2qp_04
+; CHECK: lwz [[REG:[0-9]+]], 0(5)
+; CHECK-NEXT: add [[REG1:[0-9]+]], [[REG]], [[REG1]]
+; CHECK-NEXT: mtvsrwz [[REG0:[0-9]+]], [[REG1]]
+; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG0]]
+; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @swConv2qp_testXForm(fp128* nocapture %sink,
+ i8* nocapture readonly %a) {
+entry:
+ %add.ptr = getelementptr inbounds i8, i8* %a, i64 3
+ %0 = bitcast i8* %add.ptr to i32*
+ %1 = load i32, i32* %0, align 4
+ %conv = sitofp i32 %1 to fp128
+ store fp128 %conv, fp128* %sink, align 16
+ ret void
+
+; CHECK-LABEL: swConv2qp_testXForm
+; CHECK: addi [[REG:[0-9]+]], 4, 3
+; CHECK-NEXT: lxsiwax [[REG1:[0-9]+]], 0, [[REG]]
+; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG1]]
+; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @uwConv2qp_testXForm(fp128* nocapture %sink,
+ i8* nocapture readonly %a) {
+entry:
+ %add.ptr = getelementptr inbounds i8, i8* %a, i64 3
+ %0 = bitcast i8* %add.ptr to i32*
+ %1 = load i32, i32* %0, align 4
+ %conv = uitofp i32 %1 to fp128
+ store fp128 %conv, fp128* %sink, align 16
+ ret void
+
+; CHECK-LABEL: uwConv2qp_testXForm
+; CHECK: addi [[REG:[0-9]+]], 4, 3
+; CHECK-NEXT: lxsiwzx [[REG1:[0-9]+]], 0, [[REG]]
+; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG1]]
+; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK-NEXT: blr
}
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