[PATCH] D41949: [RISCV] implement li pseudo instruction

[Alex Bradbury via Phabricator via llvm-commits]

asb added a comment.
Herald added a subscriber: edward-jones.

Ok, I've had a good think about this issue. I was slightly over-eager in committing this last night. Something like PseudoLI seems necessary for the more complex materialisation logic required for 64-bit immediates in RV64, but we can do without for RV32.  I've weighed up whether to revert and revise, or to make changes post commit

I suggest the following:

- I'll update test/CodeGen/RISCV/imm.ll so it contains tests for imm32_hi20_only which are the primary benefit of this patch for codegen
- I'll improve testing of the codegen->compression path so that we have tests that would pick up any change in the status of compression of code sequences for materialising constants
- I'll add a test for common subexpression elimination of code sequences for materializing constants, similar to Sameer's example
- I'll restore the previous imm32 pattern, add a new pattern for immediates with lo12 == 0 and remove the pattern using PseudoLI. This retains the codegen improvements and will fix the issues with compressed instruction emission.
- I'll revert the RISCVISelDAGToDAG changes as that code path is now dead. I think it's still worth having PseudoLI available to the backend as it's already an improvement over the old movImm32 code.

I have patches written for all the above, and will get going with committing them.


Repository:
  rL LLVM

https://reviews.llvm.org/D41949