[llvm] r330241 - [X86][Broadwell] Remove some unnecessary InstRW overrides and add some FIXMEs.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 17 23:41:25 PDT 2018
Author: ctopper
Date: Tue Apr 17 23:41:25 2018
New Revision: 330241
URL: http://llvm.org/viewvc/llvm-project?rev=330241&view=rev
Log:
[X86][Broadwell] Remove some unnecessary InstRW overrides and add some FIXMEs.
Modified:
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=330241&r1=330240&r2=330241&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Tue Apr 17 23:41:25 2018
@@ -401,10 +401,6 @@ def: InstRW<[BWWriteResGroup3], (instreg
"(V?)MOVUPS(Y?)rr",
"(V?)ORPD(Y?)rr",
"(V?)ORPS(Y?)rr",
- "(V?)PACKSSDW(Y?)rr",
- "(V?)PACKSSWB(Y?)rr",
- "(V?)PACKUSDW(Y?)rr",
- "(V?)PACKUSWB(Y?)rr",
"(V?)PALIGNR(Y?)rri",
"(V?)PBLENDW(Y?)rri",
"VPBROADCASTDrr",
@@ -479,19 +475,9 @@ def: InstRW<[BWWriteResGroup6], (instreg
"BTR(16|32|64)rr",
"BTS(16|32|64)ri8",
"BTS(16|32|64)rr",
- "RORX(32|64)ri",
- "SAR(8|16|32|64)r1",
- "SAR(8|16|32|64)ri",
- "SARX(32|64)rr",
"SBB(16|32|64)ri",
"SBB(16|32|64)i",
- "SBB(8|16|32|64)rr",
- "SHL(8|16|32|64)r1",
- "SHL(8|16|32|64)ri",
- "SHLX(32|64)rr",
- "SHR(8|16|32|64)r1",
- "SHR(8|16|32|64)ri",
- "SHRX(32|64)rr")>;
+ "SBB(8|16|32|64)rr")>;
def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> {
let Latency = 1;
@@ -608,20 +594,16 @@ def BWWriteResGroup9 : SchedWriteRes<[BW
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[BWWriteResGroup9], (instrs CBW, CWDE, CDQE)>;
-def: InstRW<[BWWriteResGroup9], (instregex "CLC",
- "CMC",
- "LAHF", // TODO: This doesnt match Agner's data
+def: InstRW<[BWWriteResGroup9], (instregex "LAHF", // TODO: This doesnt match Agner's data
"NOOP",
"SAHF", // TODO: This doesn't match Agner's data
"SGDT64m",
"SIDT64m",
"SLDT64m",
"SMSW16m",
- "STC",
"STRm",
"SYSCALL",
- "XCHG(16|32|64)rr")>;
+ "XCHG(16|32|64)rr")>; // FIXME: This isn't 1 uop, probably should match XCHG8rr.
def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> {
let Latency = 1;
@@ -820,8 +802,6 @@ def BWWriteResGroup27 : SchedWriteRes<[B
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[BWWriteResGroup27], (instrs IMUL16rr, IMUL32rr, IMUL32rri, IMUL32rri8, IMUL64rr, IMUL64rri32, IMUL64rri8)>;
-def: InstRW<[BWWriteResGroup27], (instrs IMUL8r, MUL8r)>;
def: InstRW<[BWWriteResGroup27], (instregex "ADD_FPrST0",
"ADD_FST0r",
"ADD_FrST0",
@@ -836,22 +816,12 @@ def: InstRW<[BWWriteResGroup27], (instre
"SUB_FPrST0",
"SUB_FST0r",
"SUB_FrST0",
- "(V?)ADDPD(Y?)rr",
- "(V?)ADDPS(Y?)rr",
- "(V?)ADDSDrr",
- "(V?)ADDSSrr",
- "(V?)ADDSUBPD(Y?)rr",
- "(V?)ADDSUBPS(Y?)rr",
"(V?)CVTDQ2PS(Y?)rr",
"(V?)CVTPS2DQ(Y?)rr",
- "(V?)CVTTPS2DQ(Y?)rr",
- "(V?)SUBPD(Y?)rr",
- "(V?)SUBPS(Y?)rr",
- "(V?)SUBSDrr",
- "(V?)SUBSSrr")>;
+ "(V?)CVTTPS2DQ(Y?)rr")>;
def BWWriteResGroup27_16 : SchedWriteRes<[BWPort1, BWPort0156]> {
- let Latency = 3;
+ let Latency = 3; // FIXME: I think this should be 4.
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
@@ -1373,11 +1343,7 @@ def BWWriteResGroup63 : SchedWriteRes<[B
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[BWWriteResGroup63], (instregex "BT(16|32|64)mi8",
- "RORX(32|64)mi",
- "SARX(32|64)rm",
- "SHLX(32|64)rm",
- "SHRX(32|64)rm")>;
+def: InstRW<[BWWriteResGroup63], (instregex "BT(16|32|64)mi8")>;
def: InstRW<[BWWriteResGroup63, ReadAfterLd], (instrs ADC8rm, ADC16rm, ADC32rm, ADC64rm,
ADCX32rm, ADCX64rm,
ADOX32rm, ADOX64rm,
@@ -1799,7 +1765,6 @@ def BWWriteResGroup91 : SchedWriteRes<[B
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[BWWriteResGroup91], (instrs IMUL32rm, IMUL32rmi, IMUL32rmi8, IMUL64rm, IMUL64rmi8, IMUL64rmi32)>;
def: InstRW<[BWWriteResGroup91], (instrs IMUL8m, MUL8m)>;
def: InstRW<[BWWriteResGroup91], (instregex "MMX_CVTPI2PSirm",
"MMX_CVTPS2PIirm",
@@ -1821,11 +1786,11 @@ def: InstRW<[BWWriteResGroup91], (instre
"(V?)SUBSSrm")>;
def BWWriteResGroup91_16 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> {
- let Latency = 8;
+ let Latency = 8; // FIXME: I think this should be 9
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[BWWriteResGroup91_16], (instrs IMUL16rm, IMUL16rmi, IMUL16rmi8)>;
+def: InstRW<[BWWriteResGroup91_16], (instrs IMUL16rm, IMUL16rmi, IMUL16rmi8)>; // TODO: Is IMUL16rm really 3 uops?
def BWWriteResGroup91_16_2 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> {
let Latency = 8;
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