[PATCH] D45635: [Power9]Legalize and emit code for truncate and convert Quad-Precision to Word

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai added inline comments.


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Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:12286
+    // STORE (FP_TO_SINT MVT::f128) is legal.
+    if (N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
+        ValidTypeForStoreFltAsInt &&
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Can we just add a condition to the check below rather than repeating most of the condition? You can even just fold the two type checks into another Boolean variable similar to `ValidTypeForStoreFltAsInt`. Furthermore, you can sink the check for the input types into the condition and exit early to prevent having to go through all the subsequent checks.


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Comment at: lib/Target/PowerPC/PPCInstrVSX.td:2515
   def XSCVQPSWZ : X_VT5_XO5_VB5<63,  9, 836, "xscvqpswz", []>;
+  def : Pat<(i32 (fp_to_sint f128:$src)),
+            (i32 (MFVSRWZ (COPY_TO_REGCLASS (XSCVQPSWZ $src), VFRC)))>;
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Can you please move the anonymous patterns to a separate section from the instruction defs?


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Comment at: test/CodeGen/PowerPC/f128-truncateNconv.ll:2
 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   -enable-ppc-quad-precision -ppc-vsr-nums-as-vr < %s | FileCheck %s
 
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I missed this on the initial review, please add `-verify-machineinstrs`.


https://reviews.llvm.org/D45635