[PATCH] D45563: [X86][AArch64][NFC] Add tests for masked merge unfolding

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai added a comment.

In https://reviews.llvm.org/D45563#1069916, @spatel wrote:

> Don't know what changes are planned here, but this is on the right track. We want to have coverage of the possible canonical IR variations for various targets.
>
> PowerPC with Altivec has a vsel instruction if you want even more coverage, but I don't think the PPC backend has the isel pattern-matching logic to produce that currently (cc @nemanjai).


Not sure this answer is pertinent any longer, but on PPC we can generate the VSX version of the vector select (`xxsel`) for rather specific situations. See `test/CodeGen/PowerPC/vselect-constants.ll` and `test/CodeGen/PowerPC/vsx.ll`.


Repository:
  rL LLVM

https://reviews.llvm.org/D45563