[PATCH] D45563: [X86][AArch64][NFC] Add tests for masked merge unfolding

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a subscriber: nemanjai.
spatel added a comment.

Don't know what changes are planned here, but this is on the right track. We want to have coverage of the possible canonical IR variations for various targets.

PowerPC with Altivec has a vsel instruction if you want even more coverage, but I don't think the PPC backend has the isel pattern-matching logic to produce that currently (cc @nemanjai).



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Comment at: test/CodeGen/X86/unfold-masked-merge-vector.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=-sse < %s | FileCheck %s --check-prefix=CHECK-NOSSE
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+sse < %s | FileCheck %s --check-prefix=CHECK-SSE
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Not sure this RUN adds much value - I think SSE is required by the x86-64 ABI, so we may already be in undefined territory with these tests. :)

A target with -mattr=avx may be slightly more interesting, but there might not be enough ISA difference there to even make that worthwhile.


Repository:
  rL LLVM

https://reviews.llvm.org/D45563