[PATCH] D45660: [RISCV] Fix assert message operator

[Mandeep Singh Grang via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL330148: [RISCV] Fix assert message operator (authored by mgrang, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D45660?vs=142535&id=142671#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D45660

Files:
  llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp


Index: llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -658,7 +658,7 @@
 
   // Handle passing f64 on RV32D with a soft float ABI.
   if (XLen == 32 && ValVT == MVT::f64) {
-    assert(!ArgFlags.isSplit() && PendingLocs.empty() ||
+    assert(!ArgFlags.isSplit() && PendingLocs.empty() &&
            "Can't lower f64 if it is split");
     // Depending on available argument GPRS, f64 may be passed in a pair of
     // GPRs, split between a GPR and the stack, or passed completely on the


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