[PATCH] D45690: [AArch64][SVE] Asm: Support for contiguous LD1 (scalar+scalar) load instructions.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen created this revision.
sdesmalen added reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro.
Herald added subscribers: kristof.beyls, tschuett.

This is patch [4/4] in a series to add assembler/disassembler support for
SVE's contiguous LD1 (scalar+scalar) instructions.


https://reviews.llvm.org/D45690

Files:
  lib/Target/AArch64/AArch64SVEInstrInfo.td
  lib/Target/AArch64/SVEInstrFormats.td
  test/MC/AArch64/SVE/ld1b-diagnostics.s
  test/MC/AArch64/SVE/ld1b.s
  test/MC/AArch64/SVE/ld1d-diagnostics.s
  test/MC/AArch64/SVE/ld1d.s
  test/MC/AArch64/SVE/ld1h-diagnostics.s
  test/MC/AArch64/SVE/ld1h.s
  test/MC/AArch64/SVE/ld1sb-diagnostics.s
  test/MC/AArch64/SVE/ld1sb.s
  test/MC/AArch64/SVE/ld1sh-diagnostics.s
  test/MC/AArch64/SVE/ld1sh.s
  test/MC/AArch64/SVE/ld1sw-diagnostics.s
  test/MC/AArch64/SVE/ld1sw.s
  test/MC/AArch64/SVE/ld1w-diagnostics.s
  test/MC/AArch64/SVE/ld1w.s

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