[PATCH] D45395: [RISCV] Implement tail call optimization

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added a comment.

Two questions.



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Comment at: lib/Target/RISCV/RISCVISelLowering.cpp:762
+  // optimize it.
+  if (Outs.size() >= 8)
+    return false;
----------------
Why? In ARM tailcall opt, it could not exceed the number of arguments due to it has no available registers for indirect call under thumb1 instructions. In RISCV, we still have temporary registers to use when the number of arguments exceeds 8.


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Comment at: lib/Target/RISCV/RISCVRegisterInfo.td:134
+def GPRTC : RegisterClass<"RISCV", [XLenVT], 32, (add
+    (sequence "X%u", 5, 7)
+  )> {
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mgrang wrote:
> Can we also use x28-x31 (Caller temporaries) here?
Could we also use x10-x17 (Argument registers)?

I think we could let RA use any registers except callee-saved registers and x0-x4.

We could not use callee-saved registers, because these registers will be restored before tailcall and the address register will be clobbered.
We could not use x0-x4, because these registers have special meaning in RISCV architecture.


Repository:
  rL LLVM

https://reviews.llvm.org/D45395