[PATCH] D45629: [X86] Add FP logical scheduler class

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: lib/Target/X86/X86InstrFPStack.td:310
 
-let SchedRW = [WriteVecLogic] in {
+let SchedRW = [WriteFLogic] in {
 defm CHS : FPUnary<fneg, MRM_E0, "fchs">;
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These look to be even more restricted than regular FP logic. For instance skylake only has them on port0 even though the xmm versions are on 3 ports. Agner's data shows them with 2 cyc latency and throughput on Jaguar. Should they be their own class?


Repository:
  rL LLVM

https://reviews.llvm.org/D45629