[llvm] r330078 - [X86] Add the bizarro movsww and movzww mnemonics for the disassembler.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Fri Apr 13 16:57:54 2018
New Revision: 330078

URL: http://llvm.org/viewvc/llvm-project?rev=330078&view=rev
Log:
[X86] Add the bizarro movsww and movzww mnemonics for the disassembler.

The destination size of the movzx/movsx instruction is controlled by the normal operand size mechanisms. Only the input type is fixed.

This means that a 0x66 prefix on the encoding for zext/sext 16->32 should really produce a 16->16 instruction. Functionally this is equivalent to a GR16->GR16 move since bits 16 and above will be preserved. So nothing is actually extended.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrExtension.td
    llvm/trunk/test/MC/Disassembler/X86/x86-32.txt

Modified: llvm/trunk/lib/Target/X86/X86InstrExtension.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrExtension.td?rev=330078&r1=330077&r2=330078&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrExtension.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrExtension.td Fri Apr 13 16:57:54 2018
@@ -89,6 +89,26 @@ def MOVZX32rm16: I<0xB7, MRMSrcMem, (out
                    [(set GR32:$dst, (zextloadi32i16 addr:$src))]>,
                    TB, OpSize32, Sched<[WriteALULd]>;
 
+// These instructions exist as a consequence of operand size prefix having
+// control of the destination size, but not the input size. Only support them
+// for the disassembler.
+let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
+def MOVSX16rr16: I<0xBF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
+                   "movs{ww|x}\t{$src, $dst|$dst, $src}",
+                   []>, TB, OpSize16, Sched<[WriteALU]>;
+def MOVZX16rr16: I<0xB7, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
+                   "movz{ww|x}\t{$src, $dst|$dst, $src}",
+                   []>, TB, OpSize16, Sched<[WriteALU]>;
+let mayLoad = 1 in {
+def MOVSX16rm16: I<0xBF, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
+                   "movs{ww|x}\t{$src, $dst|$dst, $src}",
+                   []>, OpSize16, TB, Sched<[WriteALULd]>;
+def MOVZX16rm16: I<0xB7, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
+                   "movz{ww|x}\t{$src, $dst|$dst, $src}",
+                   []>, TB, OpSize16, Sched<[WriteALULd]>;
+} // mayLoad = 1
+} // isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0
+
 // These are the same as the regular MOVZX32rr8 and MOVZX32rm8
 // except that they use GR32_NOREX for the output operand register class
 // instead of GR32. This allows them to operate on h registers on x86-64.

Modified: llvm/trunk/test/MC/Disassembler/X86/x86-32.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/x86-32.txt?rev=330078&r1=330077&r2=330078&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/x86-32.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/x86-32.txt Fri Apr 13 16:57:54 2018
@@ -829,3 +829,21 @@
 
 # CHECK: cldemote -559038737(%ebx,%ecx,8)
 0x0f,0x1c,0x84,0xcb,0xef,0xbe,0xad,0xde
+
+# CHECK: movswl %ax, %eax
+0x0f 0xbf 0xc0
+# CHECK: movsww %ax, %ax
+0x66 0x0f 0xbf 0xc0
+# CHECK: movzwl %ax, %eax
+0x0f 0xb7 0xc0
+# CHECK: movzww %ax, %ax
+0x66 0x0f 0xb7 0xc0
+
+# CHECK: movswl (%eax), %eax
+0x0f 0xbf 0x00
+# CHECK: movsww (%eax), %ax
+0x66 0x0f 0xbf 0x00
+# CHECK: movzwl (%eax), %eax
+0x0f 0xb7 0x00
+# CHECK: movzww (%eax), %ax
+0x66 0x0f 0xb7 0x00