[llvm] r330024 - [AArch64][SVE] Asm: Support for contiguous LD1 (scalar+imm) load instructions
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 13 07:41:37 PDT 2018
Author: s.desmalen
Date: Fri Apr 13 07:41:36 2018
New Revision: 330024
URL: http://llvm.org/viewvc/llvm-project?rev=330024&view=rev
Log:
[AArch64][SVE] Asm: Support for contiguous LD1 (scalar+imm) load instructions
Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro
Reviewed By: rengolin
Subscribers: tschuett, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D45618
Added:
llvm/trunk/test/MC/AArch64/SVE/ld1b-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ld1b.s
llvm/trunk/test/MC/AArch64/SVE/ld1d-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ld1d.s
llvm/trunk/test/MC/AArch64/SVE/ld1h-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ld1h.s
llvm/trunk/test/MC/AArch64/SVE/ld1sb-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ld1sb.s
llvm/trunk/test/MC/AArch64/SVE/ld1sh-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ld1sh.s
llvm/trunk/test/MC/AArch64/SVE/ld1sw-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ld1sw.s
llvm/trunk/test/MC/AArch64/SVE/ld1w-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ld1w.s
Modified:
llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.td
llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.td?rev=330024&r1=330023&r2=330024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.td Fri Apr 13 07:41:36 2018
@@ -131,6 +131,9 @@ def XZR : AArch64Reg<31, "xzr", [WZR]>
// Condition code register.
def NZCV : AArch64Reg<0, "nzcv">;
+// First fault status register
+def FFR : AArch64Reg<0, "ffr">, DwarfRegNum<[47]>;
+
// GPR register classes with the intersections of GPR32/GPR32sp and
// GPR64/GPR64sp for use by the coalescer.
def GPR32common : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 0, 30)> {
Modified: llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td?rev=330024&r1=330023&r2=330024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td Fri Apr 13 07:41:36 2018
@@ -20,6 +20,23 @@ let Predicates = [HasSVE] in {
defm ADD_ZPmZ : sve_int_bin_pred_arit_0<0b000, "add">;
defm SUB_ZPmZ : sve_int_bin_pred_arit_0<0b001, "sub">;
+ // continuous load with reg+immediate
+ defm LD1B_IMM : sve_mem_cld_si<0b0000, "ld1b", Z_b, ZPR8>;
+ defm LD1B_H_IMM : sve_mem_cld_si<0b0001, "ld1b", Z_h, ZPR16>;
+ defm LD1B_S_IMM : sve_mem_cld_si<0b0010, "ld1b", Z_s, ZPR32>;
+ defm LD1B_D_IMM : sve_mem_cld_si<0b0011, "ld1b", Z_d, ZPR64>;
+ defm LD1SW_D_IMM : sve_mem_cld_si<0b0100, "ld1sw", Z_d, ZPR64>;
+ defm LD1H_IMM : sve_mem_cld_si<0b0101, "ld1h", Z_h, ZPR16>;
+ defm LD1H_S_IMM : sve_mem_cld_si<0b0110, "ld1h", Z_s, ZPR32>;
+ defm LD1H_D_IMM : sve_mem_cld_si<0b0111, "ld1h", Z_d, ZPR64>;
+ defm LD1SH_D_IMM : sve_mem_cld_si<0b1000, "ld1sh", Z_d, ZPR64>;
+ defm LD1SH_S_IMM : sve_mem_cld_si<0b1001, "ld1sh", Z_s, ZPR32>;
+ defm LD1W_IMM : sve_mem_cld_si<0b1010, "ld1w", Z_s, ZPR32>;
+ defm LD1W_D_IMM : sve_mem_cld_si<0b1011, "ld1w", Z_d, ZPR64>;
+ defm LD1SB_D_IMM : sve_mem_cld_si<0b1100, "ld1sb", Z_d, ZPR64>;
+ defm LD1SB_S_IMM : sve_mem_cld_si<0b1101, "ld1sb", Z_s, ZPR32>;
+ defm LD1SB_H_IMM : sve_mem_cld_si<0b1110, "ld1sb", Z_h, ZPR16>;
+ defm LD1D_IMM : sve_mem_cld_si<0b1111, "ld1d", Z_d, ZPR64>;
// continuous store with immediates
defm ST1B_IMM : sve_mem_cst_si<0b00, 0b00, "st1b", Z_b, ZPR8>;
Modified: llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td?rev=330024&r1=330023&r2=330024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td Fri Apr 13 07:41:36 2018
@@ -575,3 +575,47 @@ multiclass sve_int_perm_bin_perm_pp<bits
def _S : sve_int_perm_bin_perm_pp<opc, 0b10, asm, PPR32>;
def _D : sve_int_perm_bin_perm_pp<opc, 0b11, asm, PPR64>;
}
+
+//===----------------------------------------------------------------------===//
+// SVE Memory - Contiguous Load Group
+//===----------------------------------------------------------------------===//
+
+class sve_mem_cld_si_base<bits<4> dtype, bit nf, string asm,
+ RegisterOperand VecList>
+: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4MulVl:$imm4),
+ asm, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
+ "",
+ []>, Sched<[]> {
+ bits<3> Pg;
+ bits<5> Rn;
+ bits<5> Zt;
+ bits<4> imm4;
+ let Inst{31-25} = 0b1010010;
+ let Inst{24-21} = dtype;
+ let Inst{20} = nf;
+ let Inst{19-16} = imm4;
+ let Inst{15-13} = 0b101;
+ let Inst{12-10} = Pg;
+ let Inst{9-5} = Rn;
+ let Inst{4-0} = Zt;
+
+ let mayLoad = 1;
+ let Uses = !if(!eq(nf, 1), [FFR], []);
+ let Defs = !if(!eq(nf, 1), [FFR], []);
+}
+
+multiclass sve_mem_cld_si_base<bits<4> dtype, bit nf, string asm,
+ RegisterOperand listty, ZPRRegOp zprty> {
+ def _REAL : sve_mem_cld_si_base<dtype, nf, asm, listty>;
+
+ def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
+ (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
+ def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
+ (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4MulVl:$imm4), 0>;
+ def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
+ (!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
+}
+
+multiclass sve_mem_cld_si<bits<4> dtype, string asm, RegisterOperand listty,
+ ZPRRegOp zprty>
+: sve_mem_cld_si_base<dtype, 0, asm, listty, zprty>;
\ No newline at end of file
Added: llvm/trunk/test/MC/AArch64/SVE/ld1b-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1b-diagnostics.s?rev=330024&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1b-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1b-diagnostics.s Fri Apr 13 07:41:36 2018
@@ -0,0 +1,87 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-8, 7].
+
+ld1b z23.b, p0/z, [x13, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1b z23.b, p0/z, [x13, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b z29.b, p0/z, [x3, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1b z29.b, p0/z, [x3, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b z21.h, p4/z, [x17, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1b z21.h, p4/z, [x17, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b z10.h, p5/z, [x16, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1b z10.h, p5/z, [x16, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1b z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1b z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1b z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1b z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+ld1b z27.b, p8/z, [x29, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1b z27.b, p8/z, [x29, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b z9.h, p8/z, [x25, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1b z9.h, p8/z, [x25, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1b z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1b z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+ld1b { }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: ld1b { }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b { z1.b, z2.b }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1b { z1.b, z2.b }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1b { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/ld1b.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1b.s?rev=330024&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1b.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1b.s Fri Apr 13 07:41:36 2018
@@ -0,0 +1,104 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ld1b z0.b, p0/z, [x0]
+// CHECK-INST: ld1b { z0.b }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x00,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 00 a4 <unknown>
+
+ld1b z0.h, p0/z, [x0]
+// CHECK-INST: ld1b { z0.h }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x20,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 20 a4 <unknown>
+
+ld1b z0.s, p0/z, [x0]
+// CHECK-INST: ld1b { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x40,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 40 a4 <unknown>
+
+ld1b z0.d, p0/z, [x0]
+// CHECK-INST: ld1b { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x60,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 60 a4 <unknown>
+
+ld1b { z0.b }, p0/z, [x0]
+// CHECK-INST: ld1b { z0.b }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x00,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 00 a4 <unknown>
+
+ld1b { z0.h }, p0/z, [x0]
+// CHECK-INST: ld1b { z0.h }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x20,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 20 a4 <unknown>
+
+ld1b { z0.s }, p0/z, [x0]
+// CHECK-INST: ld1b { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x40,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 40 a4 <unknown>
+
+ld1b { z0.d }, p0/z, [x0]
+// CHECK-INST: ld1b { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x60,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 60 a4 <unknown>
+
+ld1b { z31.b }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ld1b { z31.b }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x0f,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 0f a4 <unknown>
+
+ld1b { z21.b }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ld1b { z21.b }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x05,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 05 a4 <unknown>
+
+ld1b { z31.h }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ld1b { z31.h }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x2f,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 2f a4 <unknown>
+
+ld1b { z21.h }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ld1b { z21.h }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x25,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 25 a4 <unknown>
+
+ld1b { z31.s }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ld1b { z31.s }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x4f,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 4f a4 <unknown>
+
+ld1b { z21.s }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ld1b { z21.s }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x45,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 45 a4 <unknown>
+
+ld1b { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ld1b { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x6f,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 6f a4 <unknown>
+
+ld1b { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ld1b { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x65,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 65 a4 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/ld1d-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1d-diagnostics.s?rev=330024&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1d-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1d-diagnostics.s Fri Apr 13 07:41:36 2018
@@ -0,0 +1,42 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-8, 7].
+
+ld1d z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1d z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1d z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+ld1d z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1d z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+ld1d { }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: ld1d { }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d { z1.d, z2.d }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1d { z1.d, z2.d }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1d { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/ld1d.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1d.s?rev=330024&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1d.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1d.s Fri Apr 13 07:41:36 2018
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ld1d z0.d, p0/z, [x0]
+// CHECK-INST: ld1d { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xe0,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 e0 a5 <unknown>
+
+ld1d { z0.d }, p0/z, [x0]
+// CHECK-INST: ld1d { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xe0,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 e0 a5 <unknown>
+
+ld1d { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ld1d { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0xef,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf ef a5 <unknown>
+
+ld1d { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ld1d { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0xe5,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 e5 a5 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/ld1h-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1h-diagnostics.s?rev=330024&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1h-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1h-diagnostics.s Fri Apr 13 07:41:36 2018
@@ -0,0 +1,72 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-8, 7].
+
+ld1h z21.h, p4/z, [x17, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1h z21.h, p4/z, [x17, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z10.h, p5/z, [x16, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1h z10.h, p5/z, [x16, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1h z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1h z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1h z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1h z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+ld1h z9.h, p8/z, [x25, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1h z9.h, p8/z, [x25, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1h z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1h z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+ld1h { }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: ld1h { }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h { z1.h, z2.h }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1h { z1.h, z2.h }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1h { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/ld1h.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1h.s?rev=330024&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1h.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1h.s Fri Apr 13 07:41:36 2018
@@ -0,0 +1,80 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ld1h z0.h, p0/z, [x0]
+// CHECK-INST: ld1h { z0.h }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xa0,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 a0 a4 <unknown>
+
+ld1h z0.s, p0/z, [x0]
+// CHECK-INST: ld1h { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xc0,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 c0 a4 <unknown>
+
+ld1h z0.d, p0/z, [x0]
+// CHECK-INST: ld1h { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xe0,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 e0 a4 <unknown>
+
+ld1h { z0.h }, p0/z, [x0]
+// CHECK-INST: ld1h { z0.h }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xa0,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 a0 a4 <unknown>
+
+ld1h { z0.s }, p0/z, [x0]
+// CHECK-INST: ld1h { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xc0,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 c0 a4 <unknown>
+
+ld1h { z0.d }, p0/z, [x0]
+// CHECK-INST: ld1h { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xe0,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 e0 a4 <unknown>
+
+ld1h { z31.h }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ld1h { z31.h }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0xaf,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf af a4 <unknown>
+
+ld1h { z21.h }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ld1h { z21.h }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0xa5,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 a5 a4 <unknown>
+
+ld1h { z31.s }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ld1h { z31.s }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0xcf,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf cf a4 <unknown>
+
+ld1h { z21.s }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ld1h { z21.s }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0xc5,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 c5 a4 <unknown>
+
+ld1h { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ld1h { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0xef,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf ef a4 <unknown>
+
+ld1h { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ld1h { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0xe5,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 e5 a4 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/ld1sb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1sb-diagnostics.s?rev=330024&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1sb-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1sb-diagnostics.s Fri Apr 13 07:41:36 2018
@@ -0,0 +1,86 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid operand (.b)
+
+ld1sb z23.b, p0/z, [x13, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1sb z23.b, p0/z, [x13, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sb z29.b, p0/z, [x3, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1sb z29.b, p0/z, [x3, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-8, 7].
+
+ld1sb z21.h, p4/z, [x17, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sb z21.h, p4/z, [x17, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sb z10.h, p5/z, [x16, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sb z10.h, p5/z, [x16, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sb z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sb z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sb z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sb z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sb z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sb z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sb z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sb z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+ld1sb z9.h, p8/z, [x25, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1sb z9.h, p8/z, [x25, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sb z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1sb z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sb z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1sb z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+ld1sb { }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: ld1sb { }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sb { z1.h, z2.h }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1sb { z1.h, z2.h }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sb { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1sb { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/ld1sb.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1sb.s?rev=330024&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1sb.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1sb.s Fri Apr 13 07:41:36 2018
@@ -0,0 +1,80 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ld1sb z0.h, p0/z, [x0]
+// CHECK-INST: ld1sb { z0.h }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xc0,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 c0 a5 <unknown>
+
+ld1sb z0.s, p0/z, [x0]
+// CHECK-INST: ld1sb { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xa0,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 a0 a5 <unknown>
+
+ld1sb z0.d, p0/z, [x0]
+// CHECK-INST: ld1sb { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x80,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 80 a5 <unknown>
+
+ld1sb { z0.h }, p0/z, [x0]
+// CHECK-INST: ld1sb { z0.h }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xc0,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 c0 a5 <unknown>
+
+ld1sb { z0.s }, p0/z, [x0]
+// CHECK-INST: ld1sb { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0xa0,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 a0 a5 <unknown>
+
+ld1sb { z0.d }, p0/z, [x0]
+// CHECK-INST: ld1sb { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x80,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 80 a5 <unknown>
+
+ld1sb { z31.h }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ld1sb { z31.h }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0xcf,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf cf a5 <unknown>
+
+ld1sb { z21.h }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ld1sb { z21.h }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0xc5,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 c5 a5 <unknown>
+
+ld1sb { z31.s }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ld1sb { z31.s }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0xaf,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf af a5 <unknown>
+
+ld1sb { z21.s }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ld1sb { z21.s }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0xa5,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 a5 a5 <unknown>
+
+ld1sb { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ld1sb { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x8f,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 8f a5 <unknown>
+
+ld1sb { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ld1sb { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x85,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 85 a5 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/ld1sh-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1sh-diagnostics.s?rev=330024&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1sh-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1sh-diagnostics.s Fri Apr 13 07:41:36 2018
@@ -0,0 +1,71 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid operand (.h)
+
+ld1sh z23.h, p0/z, [x13, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1sh z23.h, p0/z, [x13, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh z29.h, p0/z, [x3, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1sh z29.h, p0/z, [x3, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-8, 7].
+
+ld1sh z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sh z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sh z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sh z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sh z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+ld1sh z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1sh z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1sh z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+ld1sh { }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: ld1sh { }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh { z1.s, z2.s }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1sh { z1.s, z2.s }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1sh { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/ld1sh.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1sh.s?rev=330024&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1sh.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1sh.s Fri Apr 13 07:41:36 2018
@@ -0,0 +1,56 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ld1sh z0.s, p0/z, [x0]
+// CHECK-INST: ld1sh { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x20,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 20 a5 <unknown>
+
+ld1sh z0.d, p0/z, [x0]
+// CHECK-INST: ld1sh { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x00,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 00 a5 <unknown>
+
+ld1sh { z0.s }, p0/z, [x0]
+// CHECK-INST: ld1sh { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x20,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 20 a5 <unknown>
+
+ld1sh { z0.d }, p0/z, [x0]
+// CHECK-INST: ld1sh { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x00,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 00 a5 <unknown>
+
+ld1sh { z31.s }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ld1sh { z31.s }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x2f,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 2f a5 <unknown>
+
+ld1sh { z21.s }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ld1sh { z21.s }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x25,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 25 a5 <unknown>
+
+ld1sh { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ld1sh { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x0f,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 0f a5 <unknown>
+
+ld1sh { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ld1sh { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x05,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 05 a5 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/ld1sw-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1sw-diagnostics.s?rev=330024&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1sw-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1sw-diagnostics.s Fri Apr 13 07:41:36 2018
@@ -0,0 +1,56 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid operand (.s)
+
+ld1sw z23.s, p0/z, [x13, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1sw z23.s, p0/z, [x13, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sw z29.s, p0/z, [x3, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1sw z29.s, p0/z, [x3, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-8, 7].
+
+ld1sw z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sw z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sw z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1sw z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+ld1sw z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1sw z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+ld1sw { }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: ld1sw { }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sw { z1.d, z2.d }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1sw { z1.d, z2.d }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sw { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1sw { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/ld1sw.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1sw.s?rev=330024&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1sw.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1sw.s Fri Apr 13 07:41:36 2018
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ld1sw z0.d, p0/z, [x0]
+// CHECK-INST: ld1sw { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x80,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 80 a4 <unknown>
+
+ld1sw { z0.d }, p0/z, [x0]
+// CHECK-INST: ld1sw { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x80,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 80 a4 <unknown>
+
+ld1sw { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ld1sw { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x8f,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 8f a4 <unknown>
+
+ld1sw { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ld1sw { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x85,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 85 a4 <unknown>
Added: llvm/trunk/test/MC/AArch64/SVE/ld1w-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1w-diagnostics.s?rev=330024&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1w-diagnostics.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1w-diagnostics.s Fri Apr 13 07:41:36 2018
@@ -0,0 +1,57 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-8, 7].
+
+ld1w z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1w z30.s, p6/z, [x25, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1w z29.s, p5/z, [x15, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1w z28.d, p2/z, [x28, #-9, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK-NEXT: ld1w z27.d, p1/z, [x26, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+ld1w z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1w z12.s, p8/z, [x13, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld1w z4.d, p8/z, [x11, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+ld1w { }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: ld1w { }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w { z1.s, z2.s }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1w { z1.s, z2.s }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld1w { v0.2d }, p0/z, [x1, #1, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Added: llvm/trunk/test/MC/AArch64/SVE/ld1w.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ld1w.s?rev=330024&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1w.s (added)
+++ llvm/trunk/test/MC/AArch64/SVE/ld1w.s Fri Apr 13 07:41:36 2018
@@ -0,0 +1,56 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ld1w z0.s, p0/z, [x0]
+// CHECK-INST: ld1w { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x40,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 40 a5 <unknown>
+
+ld1w z0.d, p0/z, [x0]
+// CHECK-INST: ld1w { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x60,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 60 a5 <unknown>
+
+ld1w { z0.s }, p0/z, [x0]
+// CHECK-INST: ld1w { z0.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x40,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 40 a5 <unknown>
+
+ld1w { z0.d }, p0/z, [x0]
+// CHECK-INST: ld1w { z0.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x60,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 60 a5 <unknown>
+
+ld1w { z31.s }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ld1w { z31.s }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x4f,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 4f a5 <unknown>
+
+ld1w { z21.s }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ld1w { z21.s }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x45,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 45 a5 <unknown>
+
+ld1w { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-INST: ld1w { z31.d }, p7/z, [sp, #-1, mul vl]
+// CHECK-ENCODING: [0xff,0xbf,0x6f,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 6f a5 <unknown>
+
+ld1w { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-INST: ld1w { z21.d }, p5/z, [x10, #5, mul vl]
+// CHECK-ENCODING: [0x55,0xb5,0x65,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 b5 65 a5 <unknown>
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