[llvm] r329990 - [X86] Remove the pmuldq/pmuldq intrinsics and replace with native IR.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 12 23:07:19 PDT 2018
Author: ctopper
Date: Thu Apr 12 23:07:18 2018
New Revision: 329990
URL: http://llvm.org/viewvc/llvm-project?rev=329990&view=rev
Log:
[X86] Remove the pmuldq/pmuldq intrinsics and replace with native IR.
This completes the work started in r329604 and r329605 when we changed clang to no longer use the intrinsics.
We lost some InstCombine SimplifyDemandedBit optimizations through this change as we aren't able to fold 'and', bitcast, shuffle very well.
Modified:
llvm/trunk/include/llvm/IR/IntrinsicsX86.td
llvm/trunk/lib/IR/AutoUpgrade.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp
llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86-upgrade.ll
llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86.ll
llvm/trunk/test/CodeGen/X86/avx512-intrinsics-upgrade.ll
llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll
llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll
llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll
llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll
llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll
llvm/trunk/test/CodeGen/X86/sse41-intrinsics-fast-isel.ll
llvm/trunk/test/CodeGen/X86/sse41-intrinsics-x86-upgrade.ll
llvm/trunk/test/CodeGen/X86/sse41-intrinsics-x86.ll
llvm/trunk/test/Transforms/InstCombine/X86/x86-muldq.ll
Modified: llvm/trunk/include/llvm/IR/IntrinsicsX86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsX86.td?rev=329990&r1=329989&r2=329990&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IR/IntrinsicsX86.td (original)
+++ llvm/trunk/include/llvm/IR/IntrinsicsX86.td Thu Apr 12 23:07:18 2018
@@ -408,9 +408,6 @@ let TargetPrefix = "x86" in { // All in
def int_x86_sse2_pmulh_w : GCCBuiltin<"__builtin_ia32_pmulhw128">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty,
llvm_v8i16_ty], [IntrNoMem, Commutative]>;
- def int_x86_sse2_pmulu_dq : // FIXME: remove this intrinsic
- Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty,
- llvm_v4i32_ty], [IntrNoMem, Commutative]>;
def int_x86_sse2_pmadd_wd : GCCBuiltin<"__builtin_ia32_pmaddwd128">,
Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty,
llvm_v8i16_ty], [IntrNoMem, Commutative]>;
@@ -803,13 +800,6 @@ let TargetPrefix = "x86" in { // All in
[IntrNoMem]>;
}
-// Vector multiply
-let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
- def int_x86_sse41_pmuldq : // FIXME: remove this intrinsic
- Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
- [IntrNoMem, Commutative]>;
-}
-
// Vector insert
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse41_insertps : GCCBuiltin<"__builtin_ia32_insertps128">,
@@ -1667,12 +1657,6 @@ let TargetPrefix = "x86" in { // All in
def int_x86_avx2_pmulh_w : GCCBuiltin<"__builtin_ia32_pmulhw256">,
Intrinsic<[llvm_v16i16_ty], [llvm_v16i16_ty,
llvm_v16i16_ty], [IntrNoMem, Commutative]>;
- def int_x86_avx2_pmulu_dq : // FIXME: remove this intrinsic
- Intrinsic<[llvm_v4i64_ty], [llvm_v8i32_ty,
- llvm_v8i32_ty], [IntrNoMem, Commutative]>;
- def int_x86_avx2_pmul_dq : // FIXME: remove this intrinsic
- Intrinsic<[llvm_v4i64_ty], [llvm_v8i32_ty,
- llvm_v8i32_ty], [IntrNoMem, Commutative]>;
def int_x86_avx2_pmadd_wd : GCCBuiltin<"__builtin_ia32_pmaddwd256">,
Intrinsic<[llvm_v8i32_ty], [llvm_v16i16_ty,
llvm_v16i16_ty], [IntrNoMem, Commutative]>;
@@ -4783,10 +4767,6 @@ let TargetPrefix = "x86" in {
def int_x86_avx512_mask_psubus_w_512 : GCCBuiltin<"__builtin_ia32_psubusw512_mask">,
Intrinsic<[llvm_v32i16_ty], [llvm_v32i16_ty, llvm_v32i16_ty,
llvm_v32i16_ty, llvm_i32_ty], [IntrNoMem]>;
- def int_x86_avx512_pmulu_dq_512 : // FIXME: remove this intrinsic
- Intrinsic<[llvm_v8i64_ty], [llvm_v16i32_ty, llvm_v16i32_ty], [IntrNoMem]>;
- def int_x86_avx512_pmul_dq_512 : // FIXME: remove this intrinsic
- Intrinsic<[llvm_v8i64_ty], [llvm_v16i32_ty, llvm_v16i32_ty], [IntrNoMem]>;
def int_x86_avx512_pmulhu_w_512 : GCCBuiltin<"__builtin_ia32_pmulhuw512">,
Intrinsic<[llvm_v32i16_ty], [llvm_v32i16_ty,
llvm_v32i16_ty], [IntrNoMem, Commutative]>;
Modified: llvm/trunk/lib/IR/AutoUpgrade.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/AutoUpgrade.cpp?rev=329990&r1=329989&r2=329990&view=diff
==============================================================================
--- llvm/trunk/lib/IR/AutoUpgrade.cpp (original)
+++ llvm/trunk/lib/IR/AutoUpgrade.cpp Thu Apr 12 23:07:18 2018
@@ -168,6 +168,12 @@ static bool ShouldUpgradeX86Intrinsic(Fu
Name.startswith("avx512.mask.pmull.") || // Added in 4.0
Name.startswith("avx512.mask.cvtdq2pd.") || // Added in 4.0
Name.startswith("avx512.mask.cvtudq2pd.") || // Added in 4.0
+ Name == "sse2.pmulu.dq" || // Added in 7.0
+ Name == "sse41.pmuldq" || // Added in 7.0
+ Name == "avx2.pmulu.dq" || // Added in 7.0
+ Name == "avx2.pmul.dq" || // Added in 7.0
+ Name == "avx512.pmulu.dq.512" || // Added in 7.0
+ Name == "avx512.pmul.dq.512" || // Added in 7.0
Name.startswith("avx512.mask.pmul.dq.") || // Added in 4.0
Name.startswith("avx512.mask.pmulu.dq.") || // Added in 4.0
Name.startswith("avx512.mask.pmul.hr.sw.") || // Added in 7.0
@@ -906,6 +912,35 @@ static Value *upgradeIntMinMax(IRBuilder
return Res;
}
+static Value *upgradePMULDQ(IRBuilder<> &Builder, CallInst &CI, bool IsSigned) {
+ Type *Ty = CI.getType();
+
+ // Arguments have a vXi32 type so cast to vXi64.
+ Value *LHS = Builder.CreateBitCast(CI.getArgOperand(0), Ty);
+ Value *RHS = Builder.CreateBitCast(CI.getArgOperand(1), Ty);
+
+ if (IsSigned) {
+ // Shift left then arithmetic shift right.
+ Constant *ShiftAmt = ConstantInt::get(Ty, 32);
+ LHS = Builder.CreateShl(LHS, ShiftAmt);
+ LHS = Builder.CreateAShr(LHS, ShiftAmt);
+ RHS = Builder.CreateShl(RHS, ShiftAmt);
+ RHS = Builder.CreateAShr(RHS, ShiftAmt);
+ } else {
+ // Clear the upper bits.
+ Constant *Mask = ConstantInt::get(Ty, 0xffffffff);
+ LHS = Builder.CreateAnd(LHS, Mask);
+ RHS = Builder.CreateAnd(RHS, Mask);
+ }
+
+ Value *Res = Builder.CreateMul(LHS, RHS);
+
+ if (CI.getNumArgOperands() == 4)
+ Res = EmitX86Select(Builder, CI.getArgOperand(3), Res, CI.getArgOperand(2));
+
+ return Res;
+}
+
// Applying mask on vector of i1's and make sure result is at least 8 bits wide.
static Value *ApplyX86MaskOn1BitsVec(IRBuilder<> &Builder,Value *Vec, Value *Mask,
unsigned NumElts) {
@@ -1028,24 +1063,6 @@ static bool upgradeAVX512MaskToSelect(St
IID = Intrinsic::x86_avx512_pshuf_b_512;
else
llvm_unreachable("Unexpected intrinsic");
- } else if (Name.startswith("pmul.dq.")) {
- if (VecWidth == 128)
- IID = Intrinsic::x86_sse41_pmuldq;
- else if (VecWidth == 256)
- IID = Intrinsic::x86_avx2_pmul_dq;
- else if (VecWidth == 512)
- IID = Intrinsic::x86_avx512_pmul_dq_512;
- else
- llvm_unreachable("Unexpected intrinsic");
- } else if (Name.startswith("pmulu.dq.")) {
- if (VecWidth == 128)
- IID = Intrinsic::x86_sse2_pmulu_dq;
- else if (VecWidth == 256)
- IID = Intrinsic::x86_avx2_pmulu_dq;
- else if (VecWidth == 512)
- IID = Intrinsic::x86_avx512_pmulu_dq_512;
- else
- llvm_unreachable("Unexpected intrinsic");
} else if (Name.startswith("pmul.hr.sw.")) {
if (VecWidth == 128)
IID = Intrinsic::x86_ssse3_pmul_hr_sw_128;
@@ -1455,6 +1472,16 @@ void llvm::UpgradeIntrinsicCall(CallInst
Name.startswith("avx2.pminu") ||
Name.startswith("avx512.mask.pminu"))) {
Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_ULT);
+ } else if (IsX86 && (Name == "sse2.pmulu.dq" ||
+ Name == "avx2.pmulu.dq" ||
+ Name == "avx512.pmulu.dq.512" ||
+ Name.startswith("avx512.mask.pmulu.dq."))) {
+ Rep = upgradePMULDQ(Builder, *CI, /*Signed*/false);
+ } else if (IsX86 && (Name == "sse41.pmuldq" ||
+ Name == "avx2.pmul.dq" ||
+ Name == "avx512.pmul.dq.512" ||
+ Name.startswith("avx512.mask.pmul.dq."))) {
+ Rep = upgradePMULDQ(Builder, *CI, /*Signed*/true);
} else if (IsX86 && (Name == "sse2.cvtdq2pd" ||
Name == "sse2.cvtps2pd" ||
Name == "avx.cvtdq2.pd.256" ||
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=329990&r1=329989&r2=329990&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Apr 12 23:07:18 2018
@@ -20855,24 +20855,6 @@ SDValue X86TargetLowering::LowerINTRINSI
switch (IntNo) {
default: return SDValue(); // Don't custom lower most intrinsics.
- case Intrinsic::x86_sse41_pmuldq:
- case Intrinsic::x86_avx2_pmul_dq:
- case Intrinsic::x86_avx512_pmul_dq_512: {
- MVT OpVT = Op.getSimpleValueType();
- return DAG.getNode(X86ISD::PMULDQ, dl, OpVT,
- DAG.getBitcast(OpVT, Op.getOperand(1)),
- DAG.getBitcast(OpVT, Op.getOperand(2)));
- }
-
- case Intrinsic::x86_sse2_pmulu_dq:
- case Intrinsic::x86_avx2_pmulu_dq:
- case Intrinsic::x86_avx512_pmulu_dq_512: {
- MVT OpVT = Op.getSimpleValueType();
- return DAG.getNode(X86ISD::PMULUDQ, dl, OpVT,
- DAG.getBitcast(OpVT, Op.getOperand(1)),
- DAG.getBitcast(OpVT, Op.getOperand(2)));
- }
-
case Intrinsic::x86_avx2_permd:
case Intrinsic::x86_avx2_permps:
// Operands intentionally swapped. Mask is last operand to intrinsic,
Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp?rev=329990&r1=329989&r2=329990&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp Thu Apr 12 23:07:18 2018
@@ -566,55 +566,6 @@ static Value *simplifyX86varShift(const
return Builder.CreateAShr(Vec, ShiftVec);
}
-static Value *simplifyX86muldq(const IntrinsicInst &II,
- InstCombiner::BuilderTy &Builder) {
- Value *Arg0 = II.getArgOperand(0);
- Value *Arg1 = II.getArgOperand(1);
- Type *ResTy = II.getType();
- assert(Arg0->getType()->getScalarSizeInBits() == 32 &&
- Arg1->getType()->getScalarSizeInBits() == 32 &&
- ResTy->getScalarSizeInBits() == 64 && "Unexpected muldq/muludq types");
-
- // muldq/muludq(undef, undef) -> zero (matches generic mul behavior)
- if (isa<UndefValue>(Arg0) || isa<UndefValue>(Arg1))
- return ConstantAggregateZero::get(ResTy);
-
- // Constant folding.
- // PMULDQ = (mul(vXi64 sext(shuffle<0,2,..>(Arg0)),
- // vXi64 sext(shuffle<0,2,..>(Arg1))))
- // PMULUDQ = (mul(vXi64 zext(shuffle<0,2,..>(Arg0)),
- // vXi64 zext(shuffle<0,2,..>(Arg1))))
- if (!isa<Constant>(Arg0) || !isa<Constant>(Arg1))
- return nullptr;
-
- unsigned NumElts = ResTy->getVectorNumElements();
- assert(Arg0->getType()->getVectorNumElements() == (2 * NumElts) &&
- Arg1->getType()->getVectorNumElements() == (2 * NumElts) &&
- "Unexpected muldq/muludq types");
-
- unsigned IntrinsicID = II.getIntrinsicID();
- bool IsSigned = (Intrinsic::x86_sse41_pmuldq == IntrinsicID ||
- Intrinsic::x86_avx2_pmul_dq == IntrinsicID ||
- Intrinsic::x86_avx512_pmul_dq_512 == IntrinsicID);
-
- SmallVector<unsigned, 16> ShuffleMask;
- for (unsigned i = 0; i != NumElts; ++i)
- ShuffleMask.push_back(i * 2);
-
- auto *LHS = Builder.CreateShuffleVector(Arg0, Arg0, ShuffleMask);
- auto *RHS = Builder.CreateShuffleVector(Arg1, Arg1, ShuffleMask);
-
- if (IsSigned) {
- LHS = Builder.CreateSExt(LHS, ResTy);
- RHS = Builder.CreateSExt(RHS, ResTy);
- } else {
- LHS = Builder.CreateZExt(LHS, ResTy);
- RHS = Builder.CreateZExt(RHS, ResTy);
- }
-
- return Builder.CreateMul(LHS, RHS);
-}
-
static Value *simplifyX86pack(IntrinsicInst &II, bool IsSigned) {
Value *Arg0 = II.getArgOperand(0);
Value *Arg1 = II.getArgOperand(1);
@@ -2642,26 +2593,6 @@ Instruction *InstCombiner::visitCallInst
return replaceInstUsesWith(*II, V);
break;
- case Intrinsic::x86_sse2_pmulu_dq:
- case Intrinsic::x86_sse41_pmuldq:
- case Intrinsic::x86_avx2_pmul_dq:
- case Intrinsic::x86_avx2_pmulu_dq:
- case Intrinsic::x86_avx512_pmul_dq_512:
- case Intrinsic::x86_avx512_pmulu_dq_512: {
- if (Value *V = simplifyX86muldq(*II, Builder))
- return replaceInstUsesWith(*II, V);
-
- unsigned VWidth = II->getType()->getVectorNumElements();
- APInt UndefElts(VWidth, 0);
- APInt DemandedElts = APInt::getAllOnesValue(VWidth);
- if (Value *V = SimplifyDemandedVectorElts(II, DemandedElts, UndefElts)) {
- if (V != II)
- return replaceInstUsesWith(*II, V);
- return II;
- }
- break;
- }
-
case Intrinsic::x86_sse2_packssdw_128:
case Intrinsic::x86_sse2_packsswb_128:
case Intrinsic::x86_avx2_packssdw:
Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp?rev=329990&r1=329989&r2=329990&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp Thu Apr 12 23:07:18 2018
@@ -1436,35 +1436,6 @@ Value *InstCombiner::SimplifyDemandedVec
break;
- case Intrinsic::x86_sse2_pmulu_dq:
- case Intrinsic::x86_sse41_pmuldq:
- case Intrinsic::x86_avx2_pmul_dq:
- case Intrinsic::x86_avx2_pmulu_dq:
- case Intrinsic::x86_avx512_pmul_dq_512:
- case Intrinsic::x86_avx512_pmulu_dq_512: {
- Value *Op0 = II->getArgOperand(0);
- Value *Op1 = II->getArgOperand(1);
- unsigned InnerVWidth = Op0->getType()->getVectorNumElements();
- assert((VWidth * 2) == InnerVWidth && "Unexpected input size");
-
- APInt InnerDemandedElts(InnerVWidth, 0);
- for (unsigned i = 0; i != VWidth; ++i)
- if (DemandedElts[i])
- InnerDemandedElts.setBit(i * 2);
-
- UndefElts2 = APInt(InnerVWidth, 0);
- TmpV = SimplifyDemandedVectorElts(Op0, InnerDemandedElts, UndefElts2,
- Depth + 1);
- if (TmpV) { II->setArgOperand(0, TmpV); MadeChange = true; }
-
- UndefElts3 = APInt(InnerVWidth, 0);
- TmpV = SimplifyDemandedVectorElts(Op1, InnerDemandedElts, UndefElts3,
- Depth + 1);
- if (TmpV) { II->setArgOperand(1, TmpV); MadeChange = true; }
-
- break;
- }
-
case Intrinsic::x86_sse2_packssdw_128:
case Intrinsic::x86_sse2_packsswb_128:
case Intrinsic::x86_sse2_packuswb_128:
Modified: llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86-upgrade.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86-upgrade.ll?rev=329990&r1=329989&r2=329990&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86-upgrade.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86-upgrade.ll Thu Apr 12 23:07:18 2018
@@ -5,10 +5,15 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512 --check-prefix=X64 --check-prefix=X64-AVX512
define <16 x i16> @test_x86_avx2_pblendw(<16 x i16> %a0, <16 x i16> %a1) {
-; CHECK-LABEL: test_x86_avx2_pblendw:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5,6,7],ymm1[8,9,10],ymm0[11,12,13,14,15]
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_pblendw:
+; X86: ## %bb.0:
+; X86-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5,6,7],ymm1[8,9,10],ymm0[11,12,13,14,15]
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_pblendw:
+; X64: ## %bb.0:
+; X64-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5,6,7],ymm1[8,9,10],ymm0[11,12,13,14,15]
+; X64-NEXT: retq
%res = call <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16> %a0, <16 x i16> %a1, i32 7) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -16,10 +21,15 @@ declare <16 x i16> @llvm.x86.avx2.pblend
define <4 x i32> @test_x86_avx2_pblendd_128(<4 x i32> %a0, <4 x i32> %a1) {
-; CHECK-LABEL: test_x86_avx2_pblendd_128:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3]
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_pblendd_128:
+; X86: ## %bb.0:
+; X86-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3]
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_pblendd_128:
+; X64: ## %bb.0:
+; X64-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3]
+; X64-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32> %a0, <4 x i32> %a1, i32 7) ; <<4 x i32>> [#uses=1]
ret <4 x i32> %res
}
@@ -27,10 +37,15 @@ declare <4 x i32> @llvm.x86.avx2.pblendd
define <8 x i32> @test_x86_avx2_pblendd_256(<8 x i32> %a0, <8 x i32> %a1) {
-; CHECK-LABEL: test_x86_avx2_pblendd_256:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5,6,7]
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_pblendd_256:
+; X86: ## %bb.0:
+; X86-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5,6,7]
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_pblendd_256:
+; X64: ## %bb.0:
+; X64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3,4,5,6,7]
+; X64-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32> %a0, <8 x i32> %a1, i32 7) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -42,12 +57,12 @@ define <4 x i64> @test_x86_avx2_movntdqa
; X86: ## %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: vmovntdqa (%eax), %ymm0
-; X86-NEXT: ret{{[l|q]}}
+; X86-NEXT: retl
;
; X64-LABEL: test_x86_avx2_movntdqa:
; X64: ## %bb.0:
; X64-NEXT: vmovntdqa (%rdi), %ymm0
-; X64-NEXT: ret{{[l|q]}}
+; X64-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx2.movntdqa(i8* %a0) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -55,10 +70,15 @@ declare <4 x i64> @llvm.x86.avx2.movntdq
define <16 x i16> @test_x86_avx2_mpsadbw(<32 x i8> %a0, <32 x i8> %a1) {
-; CHECK-LABEL: test_x86_avx2_mpsadbw:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vmpsadbw $7, %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_mpsadbw:
+; X86: ## %bb.0:
+; X86-NEXT: vmpsadbw $7, %ymm1, %ymm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_mpsadbw:
+; X64: ## %bb.0:
+; X64-NEXT: vmpsadbw $7, %ymm1, %ymm0, %ymm0
+; X64-NEXT: retq
%res = call <16 x i16> @llvm.x86.avx2.mpsadbw(<32 x i8> %a0, <32 x i8> %a1, i32 7) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -66,10 +86,15 @@ declare <16 x i16> @llvm.x86.avx2.mpsadb
define <4 x i64> @test_x86_avx2_psll_dq_bs(<4 x i64> %a0) {
-; CHECK-LABEL: test_x86_avx2_psll_dq_bs:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpslldq {{.*#+}} ymm0 = zero,zero,zero,zero,zero,zero,zero,ymm0[0,1,2,3,4,5,6,7,8],zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,18,19,20,21,22,23,24]
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_psll_dq_bs:
+; X86: ## %bb.0:
+; X86-NEXT: vpslldq {{.*#+}} ymm0 = zero,zero,zero,zero,zero,zero,zero,ymm0[0,1,2,3,4,5,6,7,8],zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,18,19,20,21,22,23,24]
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_psll_dq_bs:
+; X64: ## %bb.0:
+; X64-NEXT: vpslldq {{.*#+}} ymm0 = zero,zero,zero,zero,zero,zero,zero,ymm0[0,1,2,3,4,5,6,7,8],zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,18,19,20,21,22,23,24]
+; X64-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx2.psll.dq.bs(<4 x i64> %a0, i32 7) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -77,10 +102,15 @@ declare <4 x i64> @llvm.x86.avx2.psll.dq
define <4 x i64> @test_x86_avx2_psrl_dq_bs(<4 x i64> %a0) {
-; CHECK-LABEL: test_x86_avx2_psrl_dq_bs:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpsrldq {{.*#+}} ymm0 = ymm0[7,8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,ymm0[23,24,25,26,27,28,29,30,31],zero,zero,zero,zero,zero,zero,zero
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_psrl_dq_bs:
+; X86: ## %bb.0:
+; X86-NEXT: vpsrldq {{.*#+}} ymm0 = ymm0[7,8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,ymm0[23,24,25,26,27,28,29,30,31],zero,zero,zero,zero,zero,zero,zero
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_psrl_dq_bs:
+; X64: ## %bb.0:
+; X64-NEXT: vpsrldq {{.*#+}} ymm0 = ymm0[7,8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,ymm0[23,24,25,26,27,28,29,30,31],zero,zero,zero,zero,zero,zero,zero
+; X64-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx2.psrl.dq.bs(<4 x i64> %a0, i32 7) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -88,10 +118,15 @@ declare <4 x i64> @llvm.x86.avx2.psrl.dq
define <4 x i64> @test_x86_avx2_psll_dq(<4 x i64> %a0) {
-; CHECK-LABEL: test_x86_avx2_psll_dq:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpslldq {{.*#+}} ymm0 = zero,ymm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14],zero,ymm0[16,17,18,19,20,21,22,23,24,25,26,27,28,29,30]
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_psll_dq:
+; X86: ## %bb.0:
+; X86-NEXT: vpslldq {{.*#+}} ymm0 = zero,ymm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14],zero,ymm0[16,17,18,19,20,21,22,23,24,25,26,27,28,29,30]
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_psll_dq:
+; X64: ## %bb.0:
+; X64-NEXT: vpslldq {{.*#+}} ymm0 = zero,ymm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14],zero,ymm0[16,17,18,19,20,21,22,23,24,25,26,27,28,29,30]
+; X64-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx2.psll.dq(<4 x i64> %a0, i32 8) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -99,10 +134,15 @@ declare <4 x i64> @llvm.x86.avx2.psll.dq
define <4 x i64> @test_x86_avx2_psrl_dq(<4 x i64> %a0) {
-; CHECK-LABEL: test_x86_avx2_psrl_dq:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpsrldq {{.*#+}} ymm0 = ymm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],zero,ymm0[17,18,19,20,21,22,23,24,25,26,27,28,29,30,31],zero
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_psrl_dq:
+; X86: ## %bb.0:
+; X86-NEXT: vpsrldq {{.*#+}} ymm0 = ymm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],zero,ymm0[17,18,19,20,21,22,23,24,25,26,27,28,29,30,31],zero
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_psrl_dq:
+; X64: ## %bb.0:
+; X64-NEXT: vpsrldq {{.*#+}} ymm0 = ymm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],zero,ymm0[17,18,19,20,21,22,23,24,25,26,27,28,29,30,31],zero
+; X64-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx2.psrl.dq(<4 x i64> %a0, i32 8) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -110,11 +150,17 @@ declare <4 x i64> @llvm.x86.avx2.psrl.dq
define <2 x i64> @test_x86_avx2_vextracti128(<4 x i64> %a0) {
-; CHECK-LABEL: test_x86_avx2_vextracti128:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
-; CHECK-NEXT: vzeroupper
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_vextracti128:
+; X86: ## %bb.0:
+; X86-NEXT: vextractf128 $1, %ymm0, %xmm0
+; X86-NEXT: vzeroupper
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_vextracti128:
+; X64: ## %bb.0:
+; X64-NEXT: vextractf128 $1, %ymm0, %xmm0
+; X64-NEXT: vzeroupper
+; X64-NEXT: retq
%res = call <2 x i64> @llvm.x86.avx2.vextracti128(<4 x i64> %a0, i8 7)
ret <2 x i64> %res
}
@@ -122,10 +168,15 @@ declare <2 x i64> @llvm.x86.avx2.vextrac
define <4 x i64> @test_x86_avx2_vinserti128(<4 x i64> %a0, <2 x i64> %a1) {
-; CHECK-LABEL: test_x86_avx2_vinserti128:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_vinserti128:
+; X86: ## %bb.0:
+; X86-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_vinserti128:
+; X64: ## %bb.0:
+; X64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; X64-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx2.vinserti128(<4 x i64> %a0, <2 x i64> %a1, i8 7)
ret <4 x i64> %res
}
@@ -133,10 +184,15 @@ declare <4 x i64> @llvm.x86.avx2.vinsert
define <4 x double> @test_x86_avx2_vbroadcast_sd_pd_256(<2 x double> %a0) {
-; CHECK-LABEL: test_x86_avx2_vbroadcast_sd_pd_256:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vbroadcastsd %xmm0, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_vbroadcast_sd_pd_256:
+; X86: ## %bb.0:
+; X86-NEXT: vbroadcastsd %xmm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_vbroadcast_sd_pd_256:
+; X64: ## %bb.0:
+; X64-NEXT: vbroadcastsd %xmm0, %ymm0
+; X64-NEXT: retq
%res = call <4 x double> @llvm.x86.avx2.vbroadcast.sd.pd.256(<2 x double> %a0)
ret <4 x double> %res
}
@@ -144,10 +200,15 @@ declare <4 x double> @llvm.x86.avx2.vbro
define <4 x float> @test_x86_avx2_vbroadcast_ss_ps(<4 x float> %a0) {
-; CHECK-LABEL: test_x86_avx2_vbroadcast_ss_ps:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vbroadcastss %xmm0, %xmm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_vbroadcast_ss_ps:
+; X86: ## %bb.0:
+; X86-NEXT: vbroadcastss %xmm0, %xmm0
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_vbroadcast_ss_ps:
+; X64: ## %bb.0:
+; X64-NEXT: vbroadcastss %xmm0, %xmm0
+; X64-NEXT: retq
%res = call <4 x float> @llvm.x86.avx2.vbroadcast.ss.ps(<4 x float> %a0)
ret <4 x float> %res
}
@@ -155,10 +216,15 @@ declare <4 x float> @llvm.x86.avx2.vbroa
define <8 x float> @test_x86_avx2_vbroadcast_ss_ps_256(<4 x float> %a0) {
-; CHECK-LABEL: test_x86_avx2_vbroadcast_ss_ps_256:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vbroadcastss %xmm0, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_vbroadcast_ss_ps_256:
+; X86: ## %bb.0:
+; X86-NEXT: vbroadcastss %xmm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_vbroadcast_ss_ps_256:
+; X64: ## %bb.0:
+; X64-NEXT: vbroadcastss %xmm0, %ymm0
+; X64-NEXT: retq
%res = call <8 x float> @llvm.x86.avx2.vbroadcast.ss.ps.256(<4 x float> %a0)
ret <8 x float> %res
}
@@ -166,10 +232,15 @@ declare <8 x float> @llvm.x86.avx2.vbroa
define <16 x i8> @test_x86_avx2_pbroadcastb_128(<16 x i8> %a0) {
-; CHECK-LABEL: test_x86_avx2_pbroadcastb_128:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpbroadcastb %xmm0, %xmm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_pbroadcastb_128:
+; X86: ## %bb.0:
+; X86-NEXT: vpbroadcastb %xmm0, %xmm0
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_pbroadcastb_128:
+; X64: ## %bb.0:
+; X64-NEXT: vpbroadcastb %xmm0, %xmm0
+; X64-NEXT: retq
%res = call <16 x i8> @llvm.x86.avx2.pbroadcastb.128(<16 x i8> %a0)
ret <16 x i8> %res
}
@@ -177,10 +248,15 @@ declare <16 x i8> @llvm.x86.avx2.pbroadc
define <32 x i8> @test_x86_avx2_pbroadcastb_256(<16 x i8> %a0) {
-; CHECK-LABEL: test_x86_avx2_pbroadcastb_256:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpbroadcastb %xmm0, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_pbroadcastb_256:
+; X86: ## %bb.0:
+; X86-NEXT: vpbroadcastb %xmm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_pbroadcastb_256:
+; X64: ## %bb.0:
+; X64-NEXT: vpbroadcastb %xmm0, %ymm0
+; X64-NEXT: retq
%res = call <32 x i8> @llvm.x86.avx2.pbroadcastb.256(<16 x i8> %a0)
ret <32 x i8> %res
}
@@ -188,10 +264,15 @@ declare <32 x i8> @llvm.x86.avx2.pbroadc
define <8 x i16> @test_x86_avx2_pbroadcastw_128(<8 x i16> %a0) {
-; CHECK-LABEL: test_x86_avx2_pbroadcastw_128:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpbroadcastw %xmm0, %xmm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_pbroadcastw_128:
+; X86: ## %bb.0:
+; X86-NEXT: vpbroadcastw %xmm0, %xmm0
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_pbroadcastw_128:
+; X64: ## %bb.0:
+; X64-NEXT: vpbroadcastw %xmm0, %xmm0
+; X64-NEXT: retq
%res = call <8 x i16> @llvm.x86.avx2.pbroadcastw.128(<8 x i16> %a0)
ret <8 x i16> %res
}
@@ -199,10 +280,15 @@ declare <8 x i16> @llvm.x86.avx2.pbroadc
define <16 x i16> @test_x86_avx2_pbroadcastw_256(<8 x i16> %a0) {
-; CHECK-LABEL: test_x86_avx2_pbroadcastw_256:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpbroadcastw %xmm0, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_pbroadcastw_256:
+; X86: ## %bb.0:
+; X86-NEXT: vpbroadcastw %xmm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_pbroadcastw_256:
+; X64: ## %bb.0:
+; X64-NEXT: vpbroadcastw %xmm0, %ymm0
+; X64-NEXT: retq
%res = call <16 x i16> @llvm.x86.avx2.pbroadcastw.256(<8 x i16> %a0)
ret <16 x i16> %res
}
@@ -210,10 +296,15 @@ declare <16 x i16> @llvm.x86.avx2.pbroad
define <4 x i32> @test_x86_avx2_pbroadcastd_128(<4 x i32> %a0) {
-; CHECK-LABEL: test_x86_avx2_pbroadcastd_128:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vbroadcastss %xmm0, %xmm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_pbroadcastd_128:
+; X86: ## %bb.0:
+; X86-NEXT: vbroadcastss %xmm0, %xmm0
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_pbroadcastd_128:
+; X64: ## %bb.0:
+; X64-NEXT: vbroadcastss %xmm0, %xmm0
+; X64-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx2.pbroadcastd.128(<4 x i32> %a0)
ret <4 x i32> %res
}
@@ -221,10 +312,15 @@ declare <4 x i32> @llvm.x86.avx2.pbroadc
define <8 x i32> @test_x86_avx2_pbroadcastd_256(<4 x i32> %a0) {
-; CHECK-LABEL: test_x86_avx2_pbroadcastd_256:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vbroadcastss %xmm0, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_pbroadcastd_256:
+; X86: ## %bb.0:
+; X86-NEXT: vbroadcastss %xmm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_pbroadcastd_256:
+; X64: ## %bb.0:
+; X64-NEXT: vbroadcastss %xmm0, %ymm0
+; X64-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx2.pbroadcastd.256(<4 x i32> %a0)
ret <8 x i32> %res
}
@@ -232,10 +328,15 @@ declare <8 x i32> @llvm.x86.avx2.pbroadc
define <2 x i64> @test_x86_avx2_pbroadcastq_128(<2 x i64> %a0) {
-; CHECK-LABEL: test_x86_avx2_pbroadcastq_128:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpbroadcastq %xmm0, %xmm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_pbroadcastq_128:
+; X86: ## %bb.0:
+; X86-NEXT: vpbroadcastq %xmm0, %xmm0
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_pbroadcastq_128:
+; X64: ## %bb.0:
+; X64-NEXT: vpbroadcastq %xmm0, %xmm0
+; X64-NEXT: retq
%res = call <2 x i64> @llvm.x86.avx2.pbroadcastq.128(<2 x i64> %a0)
ret <2 x i64> %res
}
@@ -243,10 +344,15 @@ declare <2 x i64> @llvm.x86.avx2.pbroadc
define <4 x i64> @test_x86_avx2_pbroadcastq_256(<2 x i64> %a0) {
-; CHECK-LABEL: test_x86_avx2_pbroadcastq_256:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vbroadcastsd %xmm0, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_pbroadcastq_256:
+; X86: ## %bb.0:
+; X86-NEXT: vbroadcastsd %xmm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_pbroadcastq_256:
+; X64: ## %bb.0:
+; X64-NEXT: vbroadcastsd %xmm0, %ymm0
+; X64-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx2.pbroadcastq.256(<2 x i64> %a0)
ret <4 x i64> %res
}
@@ -254,10 +360,15 @@ declare <4 x i64> @llvm.x86.avx2.pbroadc
define <8 x i32> @test_x86_avx2_pmovsxbd(<16 x i8> %a0) {
-; CHECK-LABEL: test_x86_avx2_pmovsxbd:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmovsxbd %xmm0, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_pmovsxbd:
+; X86: ## %bb.0:
+; X86-NEXT: vpmovsxbd %xmm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_pmovsxbd:
+; X64: ## %bb.0:
+; X64-NEXT: vpmovsxbd %xmm0, %ymm0
+; X64-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx2.pmovsxbd(<16 x i8> %a0) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -265,10 +376,15 @@ declare <8 x i32> @llvm.x86.avx2.pmovsxb
define <4 x i64> @test_x86_avx2_pmovsxbq(<16 x i8> %a0) {
-; CHECK-LABEL: test_x86_avx2_pmovsxbq:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmovsxbq %xmm0, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_pmovsxbq:
+; X86: ## %bb.0:
+; X86-NEXT: vpmovsxbq %xmm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_pmovsxbq:
+; X64: ## %bb.0:
+; X64-NEXT: vpmovsxbq %xmm0, %ymm0
+; X64-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx2.pmovsxbq(<16 x i8> %a0) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -276,10 +392,15 @@ declare <4 x i64> @llvm.x86.avx2.pmovsxb
define <16 x i16> @test_x86_avx2_pmovsxbw(<16 x i8> %a0) {
-; CHECK-LABEL: test_x86_avx2_pmovsxbw:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmovsxbw %xmm0, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_pmovsxbw:
+; X86: ## %bb.0:
+; X86-NEXT: vpmovsxbw %xmm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_pmovsxbw:
+; X64: ## %bb.0:
+; X64-NEXT: vpmovsxbw %xmm0, %ymm0
+; X64-NEXT: retq
%res = call <16 x i16> @llvm.x86.avx2.pmovsxbw(<16 x i8> %a0) ; <<8 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -287,10 +408,15 @@ declare <16 x i16> @llvm.x86.avx2.pmovsx
define <4 x i64> @test_x86_avx2_pmovsxdq(<4 x i32> %a0) {
-; CHECK-LABEL: test_x86_avx2_pmovsxdq:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmovsxdq %xmm0, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_pmovsxdq:
+; X86: ## %bb.0:
+; X86-NEXT: vpmovsxdq %xmm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_pmovsxdq:
+; X64: ## %bb.0:
+; X64-NEXT: vpmovsxdq %xmm0, %ymm0
+; X64-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx2.pmovsxdq(<4 x i32> %a0) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -298,10 +424,15 @@ declare <4 x i64> @llvm.x86.avx2.pmovsxd
define <8 x i32> @test_x86_avx2_pmovsxwd(<8 x i16> %a0) {
-; CHECK-LABEL: test_x86_avx2_pmovsxwd:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmovsxwd %xmm0, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_pmovsxwd:
+; X86: ## %bb.0:
+; X86-NEXT: vpmovsxwd %xmm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_pmovsxwd:
+; X64: ## %bb.0:
+; X64-NEXT: vpmovsxwd %xmm0, %ymm0
+; X64-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx2.pmovsxwd(<8 x i16> %a0) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -309,10 +440,15 @@ declare <8 x i32> @llvm.x86.avx2.pmovsxw
define <4 x i64> @test_x86_avx2_pmovsxwq(<8 x i16> %a0) {
-; CHECK-LABEL: test_x86_avx2_pmovsxwq:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmovsxwq %xmm0, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_pmovsxwq:
+; X86: ## %bb.0:
+; X86-NEXT: vpmovsxwq %xmm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_pmovsxwq:
+; X64: ## %bb.0:
+; X64-NEXT: vpmovsxwq %xmm0, %ymm0
+; X64-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx2.pmovsxwq(<8 x i16> %a0) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -320,10 +456,15 @@ declare <4 x i64> @llvm.x86.avx2.pmovsxw
define <8 x i32> @test_x86_avx2_pmovzxbd(<16 x i8> %a0) {
-; CHECK-LABEL: test_x86_avx2_pmovzxbd:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_pmovzxbd:
+; X86: ## %bb.0:
+; X86-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_pmovzxbd:
+; X64: ## %bb.0:
+; X64-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
+; X64-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx2.pmovzxbd(<16 x i8> %a0) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -331,10 +472,15 @@ declare <8 x i32> @llvm.x86.avx2.pmovzxb
define <4 x i64> @test_x86_avx2_pmovzxbq(<16 x i8> %a0) {
-; CHECK-LABEL: test_x86_avx2_pmovzxbq:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmovzxbq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero,xmm0[2],zero,zero,zero,zero,zero,zero,zero,xmm0[3],zero,zero,zero,zero,zero,zero,zero
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_pmovzxbq:
+; X86: ## %bb.0:
+; X86-NEXT: vpmovzxbq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero,xmm0[2],zero,zero,zero,zero,zero,zero,zero,xmm0[3],zero,zero,zero,zero,zero,zero,zero
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_pmovzxbq:
+; X64: ## %bb.0:
+; X64-NEXT: vpmovzxbq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero,xmm0[2],zero,zero,zero,zero,zero,zero,zero,xmm0[3],zero,zero,zero,zero,zero,zero,zero
+; X64-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx2.pmovzxbq(<16 x i8> %a0) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -342,10 +488,15 @@ declare <4 x i64> @llvm.x86.avx2.pmovzxb
define <16 x i16> @test_x86_avx2_pmovzxbw(<16 x i8> %a0) {
-; CHECK-LABEL: test_x86_avx2_pmovzxbw:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_pmovzxbw:
+; X86: ## %bb.0:
+; X86-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_pmovzxbw:
+; X64: ## %bb.0:
+; X64-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
+; X64-NEXT: retq
%res = call <16 x i16> @llvm.x86.avx2.pmovzxbw(<16 x i8> %a0) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -353,10 +504,15 @@ declare <16 x i16> @llvm.x86.avx2.pmovzx
define <4 x i64> @test_x86_avx2_pmovzxdq(<4 x i32> %a0) {
-; CHECK-LABEL: test_x86_avx2_pmovzxdq:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_pmovzxdq:
+; X86: ## %bb.0:
+; X86-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_pmovzxdq:
+; X64: ## %bb.0:
+; X64-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
+; X64-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx2.pmovzxdq(<4 x i32> %a0) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -364,10 +520,15 @@ declare <4 x i64> @llvm.x86.avx2.pmovzxd
define <8 x i32> @test_x86_avx2_pmovzxwd(<8 x i16> %a0) {
-; CHECK-LABEL: test_x86_avx2_pmovzxwd:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_pmovzxwd:
+; X86: ## %bb.0:
+; X86-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_pmovzxwd:
+; X64: ## %bb.0:
+; X64-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
+; X64-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx2.pmovzxwd(<8 x i16> %a0) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -375,10 +536,15 @@ declare <8 x i32> @llvm.x86.avx2.pmovzxw
define <4 x i64> @test_x86_avx2_pmovzxwq(<8 x i16> %a0) {
-; CHECK-LABEL: test_x86_avx2_pmovzxwq:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmovzxwq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_pmovzxwq:
+; X86: ## %bb.0:
+; X86-NEXT: vpmovzxwq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_pmovzxwq:
+; X64: ## %bb.0:
+; X64-NEXT: vpmovzxwq {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
+; X64-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx2.pmovzxwq(<8 x i16> %a0) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -394,7 +560,7 @@ define void @test_x86_avx_storeu_dq_256(
; X86-NEXT: vpsubb %ymm1, %ymm0, %ymm0
; X86-NEXT: vmovdqu %ymm0, (%eax)
; X86-NEXT: vzeroupper
-; X86-NEXT: ret{{[l|q]}}
+; X86-NEXT: retl
;
; X64-LABEL: test_x86_avx_storeu_dq_256:
; X64: ## %bb.0:
@@ -402,7 +568,7 @@ define void @test_x86_avx_storeu_dq_256(
; X64-NEXT: vpsubb %ymm1, %ymm0, %ymm0
; X64-NEXT: vmovdqu %ymm0, (%rdi)
; X64-NEXT: vzeroupper
-; X64-NEXT: ret{{[l|q]}}
+; X64-NEXT: retq
%a2 = add <32 x i8> %a1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
call void @llvm.x86.avx.storeu.dq.256(i8* %a0, <32 x i8> %a2)
ret void
@@ -410,160 +576,240 @@ define void @test_x86_avx_storeu_dq_256(
declare void @llvm.x86.avx.storeu.dq.256(i8*, <32 x i8>) nounwind
define <32 x i8> @mm256_max_epi8(<32 x i8> %a0, <32 x i8> %a1) {
-; CHECK-LABEL: mm256_max_epi8:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: mm256_max_epi8:
+; X86: ## %bb.0:
+; X86-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: mm256_max_epi8:
+; X64: ## %bb.0:
+; X64-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0
+; X64-NEXT: retq
%res = call <32 x i8> @llvm.x86.avx2.pmaxs.b(<32 x i8> %a0, <32 x i8> %a1)
ret <32 x i8> %res
}
declare <32 x i8> @llvm.x86.avx2.pmaxs.b(<32 x i8>, <32 x i8>) nounwind readnone
define <16 x i16> @mm256_max_epi16(<16 x i16> %a0, <16 x i16> %a1) {
-; CHECK-LABEL: mm256_max_epi16:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: mm256_max_epi16:
+; X86: ## %bb.0:
+; X86-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: mm256_max_epi16:
+; X64: ## %bb.0:
+; X64-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0
+; X64-NEXT: retq
%res = call <16 x i16> @llvm.x86.avx2.pmaxs.w(<16 x i16> %a0, <16 x i16> %a1)
ret <16 x i16> %res
}
declare <16 x i16> @llvm.x86.avx2.pmaxs.w(<16 x i16>, <16 x i16>) nounwind readnone
define <8 x i32> @mm256_max_epi32(<8 x i32> %a0, <8 x i32> %a1) {
-; CHECK-LABEL: mm256_max_epi32:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: mm256_max_epi32:
+; X86: ## %bb.0:
+; X86-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: mm256_max_epi32:
+; X64: ## %bb.0:
+; X64-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
+; X64-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx2.pmaxs.d(<8 x i32> %a0, <8 x i32> %a1)
ret <8 x i32> %res
}
declare <8 x i32> @llvm.x86.avx2.pmaxs.d(<8 x i32>, <8 x i32>) nounwind readnone
define <32 x i8> @mm256_max_epu8(<32 x i8> %a0, <32 x i8> %a1) {
-; CHECK-LABEL: mm256_max_epu8:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmaxub %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: mm256_max_epu8:
+; X86: ## %bb.0:
+; X86-NEXT: vpmaxub %ymm1, %ymm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: mm256_max_epu8:
+; X64: ## %bb.0:
+; X64-NEXT: vpmaxub %ymm1, %ymm0, %ymm0
+; X64-NEXT: retq
%res = call <32 x i8> @llvm.x86.avx2.pmaxu.b(<32 x i8> %a0, <32 x i8> %a1)
ret <32 x i8> %res
}
declare <32 x i8> @llvm.x86.avx2.pmaxu.b(<32 x i8>, <32 x i8>) nounwind readnone
define <16 x i16> @mm256_max_epu16(<16 x i16> %a0, <16 x i16> %a1) {
-; CHECK-LABEL: mm256_max_epu16:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: mm256_max_epu16:
+; X86: ## %bb.0:
+; X86-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: mm256_max_epu16:
+; X64: ## %bb.0:
+; X64-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0
+; X64-NEXT: retq
%res = call <16 x i16> @llvm.x86.avx2.pmaxu.w(<16 x i16> %a0, <16 x i16> %a1)
ret <16 x i16> %res
}
declare <16 x i16> @llvm.x86.avx2.pmaxu.w(<16 x i16>, <16 x i16>) nounwind readnone
define <8 x i32> @mm256_max_epu32(<8 x i32> %a0, <8 x i32> %a1) {
-; CHECK-LABEL: mm256_max_epu32:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmaxud %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: mm256_max_epu32:
+; X86: ## %bb.0:
+; X86-NEXT: vpmaxud %ymm1, %ymm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: mm256_max_epu32:
+; X64: ## %bb.0:
+; X64-NEXT: vpmaxud %ymm1, %ymm0, %ymm0
+; X64-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx2.pmaxu.d(<8 x i32> %a0, <8 x i32> %a1)
ret <8 x i32> %res
}
declare <8 x i32> @llvm.x86.avx2.pmaxu.d(<8 x i32>, <8 x i32>) nounwind readnone
define <32 x i8> @mm256_min_epi8(<32 x i8> %a0, <32 x i8> %a1) {
-; CHECK-LABEL: mm256_min_epi8:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpminsb %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: mm256_min_epi8:
+; X86: ## %bb.0:
+; X86-NEXT: vpminsb %ymm1, %ymm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: mm256_min_epi8:
+; X64: ## %bb.0:
+; X64-NEXT: vpminsb %ymm1, %ymm0, %ymm0
+; X64-NEXT: retq
%res = call <32 x i8> @llvm.x86.avx2.pmins.b(<32 x i8> %a0, <32 x i8> %a1)
ret <32 x i8> %res
}
declare <32 x i8> @llvm.x86.avx2.pmins.b(<32 x i8>, <32 x i8>) nounwind readnone
define <16 x i16> @mm256_min_epi16(<16 x i16> %a0, <16 x i16> %a1) {
-; CHECK-LABEL: mm256_min_epi16:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpminsw %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: mm256_min_epi16:
+; X86: ## %bb.0:
+; X86-NEXT: vpminsw %ymm1, %ymm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: mm256_min_epi16:
+; X64: ## %bb.0:
+; X64-NEXT: vpminsw %ymm1, %ymm0, %ymm0
+; X64-NEXT: retq
%res = call <16 x i16> @llvm.x86.avx2.pmins.w(<16 x i16> %a0, <16 x i16> %a1)
ret <16 x i16> %res
}
declare <16 x i16> @llvm.x86.avx2.pmins.w(<16 x i16>, <16 x i16>) nounwind readnone
define <8 x i32> @mm256_min_epi32(<8 x i32> %a0, <8 x i32> %a1) {
-; CHECK-LABEL: mm256_min_epi32:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpminsd %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: mm256_min_epi32:
+; X86: ## %bb.0:
+; X86-NEXT: vpminsd %ymm1, %ymm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: mm256_min_epi32:
+; X64: ## %bb.0:
+; X64-NEXT: vpminsd %ymm1, %ymm0, %ymm0
+; X64-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx2.pmins.d(<8 x i32> %a0, <8 x i32> %a1)
ret <8 x i32> %res
}
declare <8 x i32> @llvm.x86.avx2.pmins.d(<8 x i32>, <8 x i32>) nounwind readnone
define <32 x i8> @mm256_min_epu8(<32 x i8> %a0, <32 x i8> %a1) {
-; CHECK-LABEL: mm256_min_epu8:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpminub %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: mm256_min_epu8:
+; X86: ## %bb.0:
+; X86-NEXT: vpminub %ymm1, %ymm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: mm256_min_epu8:
+; X64: ## %bb.0:
+; X64-NEXT: vpminub %ymm1, %ymm0, %ymm0
+; X64-NEXT: retq
%res = call <32 x i8> @llvm.x86.avx2.pminu.b(<32 x i8> %a0, <32 x i8> %a1)
ret <32 x i8> %res
}
declare <32 x i8> @llvm.x86.avx2.pminu.b(<32 x i8>, <32 x i8>) nounwind readnone
define <16 x i16> @mm256_min_epu16(<16 x i16> %a0, <16 x i16> %a1) {
-; CHECK-LABEL: mm256_min_epu16:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpminuw %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: mm256_min_epu16:
+; X86: ## %bb.0:
+; X86-NEXT: vpminuw %ymm1, %ymm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: mm256_min_epu16:
+; X64: ## %bb.0:
+; X64-NEXT: vpminuw %ymm1, %ymm0, %ymm0
+; X64-NEXT: retq
%res = call <16 x i16> @llvm.x86.avx2.pminu.w(<16 x i16> %a0, <16 x i16> %a1)
ret <16 x i16> %res
}
declare <16 x i16> @llvm.x86.avx2.pminu.w(<16 x i16>, <16 x i16>) nounwind readnone
define <8 x i32> @mm256_min_epu32(<8 x i32> %a0, <8 x i32> %a1) {
-; CHECK-LABEL: mm256_min_epu32:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpminud %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: mm256_min_epu32:
+; X86: ## %bb.0:
+; X86-NEXT: vpminud %ymm1, %ymm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: mm256_min_epu32:
+; X64: ## %bb.0:
+; X64-NEXT: vpminud %ymm1, %ymm0, %ymm0
+; X64-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx2.pminu.d(<8 x i32> %a0, <8 x i32> %a1)
ret <8 x i32> %res
}
declare <8 x i32> @llvm.x86.avx2.pminu.d(<8 x i32>, <8 x i32>) nounwind readnone
define <32 x i8> @mm256_avg_epu8(<32 x i8> %a0, <32 x i8> %a1) {
-; CHECK-LABEL: mm256_avg_epu8:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpavgb %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: mm256_avg_epu8:
+; X86: ## %bb.0:
+; X86-NEXT: vpavgb %ymm1, %ymm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: mm256_avg_epu8:
+; X64: ## %bb.0:
+; X64-NEXT: vpavgb %ymm1, %ymm0, %ymm0
+; X64-NEXT: retq
%res = call <32 x i8> @llvm.x86.avx2.pavg.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
declare <32 x i8> @llvm.x86.avx2.pavg.b(<32 x i8>, <32 x i8>) nounwind readnone
define <16 x i16> @mm256_avg_epu16(<16 x i16> %a0, <16 x i16> %a1) {
-; CHECK-LABEL: mm256_avg_epu16:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpavgw %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: mm256_avg_epu16:
+; X86: ## %bb.0:
+; X86-NEXT: vpavgw %ymm1, %ymm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: mm256_avg_epu16:
+; X64: ## %bb.0:
+; X64-NEXT: vpavgw %ymm1, %ymm0, %ymm0
+; X64-NEXT: retq
%res = call <16 x i16> @llvm.x86.avx2.pavg.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
declare <16 x i16> @llvm.x86.avx2.pavg.w(<16 x i16>, <16 x i16>) nounwind readnone
define <32 x i8> @test_x86_avx2_pabs_b(<32 x i8> %a0) {
-; CHECK-LABEL: test_x86_avx2_pabs_b:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpabsb %ymm0, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_pabs_b:
+; X86: ## %bb.0:
+; X86-NEXT: vpabsb %ymm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_pabs_b:
+; X64: ## %bb.0:
+; X64-NEXT: vpabsb %ymm0, %ymm0
+; X64-NEXT: retq
%res = call <32 x i8> @llvm.x86.avx2.pabs.b(<32 x i8> %a0) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
declare <32 x i8> @llvm.x86.avx2.pabs.b(<32 x i8>) nounwind readnone
define <8 x i32> @test_x86_avx2_pabs_d(<8 x i32> %a0) {
-; CHECK-LABEL: test_x86_avx2_pabs_d:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpabsd %ymm0, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_pabs_d:
+; X86: ## %bb.0:
+; X86-NEXT: vpabsd %ymm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_pabs_d:
+; X64: ## %bb.0:
+; X64-NEXT: vpabsd %ymm0, %ymm0
+; X64-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx2.pabs.d(<8 x i32> %a0) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -571,10 +817,15 @@ declare <8 x i32> @llvm.x86.avx2.pabs.d(
define <16 x i16> @test_x86_avx2_pabs_w(<16 x i16> %a0) {
-; CHECK-LABEL: test_x86_avx2_pabs_w:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpabsw %ymm0, %ymm0
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_pabs_w:
+; X86: ## %bb.0:
+; X86-NEXT: vpabsw %ymm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_pabs_w:
+; X64: ## %bb.0:
+; X64-NEXT: vpabsw %ymm0, %ymm0
+; X64-NEXT: retq
%res = call <16 x i16> @llvm.x86.avx2.pabs.w(<16 x i16> %a0) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -582,11 +833,48 @@ declare <16 x i16> @llvm.x86.avx2.pabs.w
define <4 x i64> @test_x86_avx2_vperm2i128(<4 x i64> %a0, <4 x i64> %a1) {
-; CHECK-LABEL: test_x86_avx2_vperm2i128:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[2,3,0,1]
-; CHECK-NEXT: ret{{[l|q]}}
+; X86-LABEL: test_x86_avx2_vperm2i128:
+; X86: ## %bb.0:
+; X86-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[2,3,0,1]
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_vperm2i128:
+; X64: ## %bb.0:
+; X64-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[2,3,0,1]
+; X64-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx2.vperm2i128(<4 x i64> %a0, <4 x i64> %a1, i8 1) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
declare <4 x i64> @llvm.x86.avx2.vperm2i128(<4 x i64>, <4 x i64>, i8) nounwind readonly
+
+
+define <4 x i64> @test_x86_avx2_pmulu_dq(<8 x i32> %a0, <8 x i32> %a1) {
+; X86-LABEL: test_x86_avx2_pmulu_dq:
+; X86: ## %bb.0:
+; X86-NEXT: vpmuludq %ymm1, %ymm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_pmulu_dq:
+; X64: ## %bb.0:
+; X64-NEXT: vpmuludq %ymm1, %ymm0, %ymm0
+; X64-NEXT: retq
+ %res = call <4 x i64> @llvm.x86.avx2.pmulu.dq(<8 x i32> %a0, <8 x i32> %a1) ; <<4 x i64>> [#uses=1]
+ ret <4 x i64> %res
+}
+declare <4 x i64> @llvm.x86.avx2.pmulu.dq(<8 x i32>, <8 x i32>) nounwind readnone
+
+
+define <4 x i64> @test_x86_avx2_pmul_dq(<8 x i32> %a0, <8 x i32> %a1) {
+; X86-LABEL: test_x86_avx2_pmul_dq:
+; X86: ## %bb.0:
+; X86-NEXT: vpmuldq %ymm1, %ymm0, %ymm0
+; X86-NEXT: retl
+;
+; X64-LABEL: test_x86_avx2_pmul_dq:
+; X64: ## %bb.0:
+; X64-NEXT: vpmuldq %ymm1, %ymm0, %ymm0
+; X64-NEXT: retq
+ %res = call <4 x i64> @llvm.x86.avx2.pmul.dq(<8 x i32> %a0, <8 x i32> %a1) ; <<4 x i64>> [#uses=1]
+ ret <4 x i64> %res
+}
+declare <4 x i64> @llvm.x86.avx2.pmul.dq(<8 x i32>, <8 x i32>) nounwind readnone
Modified: llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86.ll?rev=329990&r1=329989&r2=329990&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx2-intrinsics-x86.ll Thu Apr 12 23:07:18 2018
@@ -5,15 +5,25 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512f,+avx512bw,+avx512vl,+avx512dq -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512VL --check-prefix=X64 --check-prefix=X64-AVX512VL
define <16 x i16> @test_x86_avx2_packssdw(<8 x i32> %a0, <8 x i32> %a1) {
-; AVX2-LABEL: test_x86_avx2_packssdw:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpackssdw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x6b,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_packssdw:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpackssdw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6b,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_packssdw:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpackssdw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x6b,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_packssdw:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpackssdw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6b,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_packssdw:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpackssdw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x6b,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_packssdw:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpackssdw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6b,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> %a0, <8 x i32> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -26,43 +36,53 @@ define <16 x i16> @test_x86_avx2_packssd
; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,0,255,32767,32767,65535,0,0,0,0,32769,32768,0,65280]
; X86-AVX-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
; X86-AVX-NEXT: ## fixup A - offset: 4, value: LCPI1_0, kind: FK_Data_4
-; X86-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
;
; X86-AVX512VL-LABEL: test_x86_avx2_packssdw_fold:
; X86-AVX512VL: ## %bb.0:
; X86-AVX512VL-NEXT: vmovaps LCPI1_0, %ymm0 ## EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,32767,65535,0,0,0,0,32769,32768,0,65280]
; X86-AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
; X86-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI1_0, kind: FK_Data_4
-; X86-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
;
; X64-AVX-LABEL: test_x86_avx2_packssdw_fold:
; X64-AVX: ## %bb.0:
; X64-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,0,255,32767,32767,65535,0,0,0,0,32769,32768,0,65280]
; X64-AVX-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
; X64-AVX-NEXT: ## fixup A - offset: 4, value: LCPI1_0-4, kind: reloc_riprel_4byte
-; X64-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
;
; X64-AVX512VL-LABEL: test_x86_avx2_packssdw_fold:
; X64-AVX512VL: ## %bb.0:
; X64-AVX512VL-NEXT: vmovaps {{.*}}(%rip), %ymm0 ## EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,32767,65535,0,0,0,0,32769,32768,0,65280]
; X64-AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
; X64-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI1_0-4, kind: reloc_riprel_4byte
-; X64-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> zeroinitializer, <8 x i32> <i32 255, i32 32767, i32 65535, i32 -1, i32 -32767, i32 -65535, i32 0, i32 -256>)
ret <16 x i16> %res
}
define <32 x i8> @test_x86_avx2_packsswb(<16 x i16> %a0, <16 x i16> %a1) {
-; AVX2-LABEL: test_x86_avx2_packsswb:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpacksswb %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x63,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_packsswb:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpacksswb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x63,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_packsswb:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpacksswb %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x63,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_packsswb:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpacksswb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x63,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_packsswb:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpacksswb %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x63,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_packsswb:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpacksswb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x63,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> %a0, <16 x i16> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
@@ -75,43 +95,53 @@ define <32 x i8> @test_x86_avx2_packsswb
; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0,0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
; X86-AVX-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
; X86-AVX-NEXT: ## fixup A - offset: 4, value: LCPI3_0, kind: FK_Data_4
-; X86-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
;
; X86-AVX512VL-LABEL: test_x86_avx2_packsswb_fold:
; X86-AVX512VL: ## %bb.0:
; X86-AVX512VL-NEXT: vmovaps LCPI3_0, %ymm0 ## EVEX TO VEX Compression ymm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0,0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
; X86-AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
; X86-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI3_0, kind: FK_Data_4
-; X86-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
;
; X64-AVX-LABEL: test_x86_avx2_packsswb_fold:
; X64-AVX: ## %bb.0:
; X64-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0,0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
; X64-AVX-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
; X64-AVX-NEXT: ## fixup A - offset: 4, value: LCPI3_0-4, kind: reloc_riprel_4byte
-; X64-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
;
; X64-AVX512VL-LABEL: test_x86_avx2_packsswb_fold:
; X64-AVX512VL: ## %bb.0:
; X64-AVX512VL-NEXT: vmovaps {{.*}}(%rip), %ymm0 ## EVEX TO VEX Compression ymm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0,0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
; X64-AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
; X64-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI3_0-4, kind: reloc_riprel_4byte
-; X64-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> <i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678, i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678>, <16 x i16> zeroinitializer)
ret <32 x i8> %res
}
define <32 x i8> @test_x86_avx2_packuswb(<16 x i16> %a0, <16 x i16> %a1) {
-; AVX2-LABEL: test_x86_avx2_packuswb:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpackuswb %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x67,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_packuswb:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpackuswb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x67,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_packuswb:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpackuswb %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x67,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_packuswb:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpackuswb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x67,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_packuswb:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpackuswb %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x67,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_packuswb:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpackuswb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x67,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> %a0, <16 x i16> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
@@ -124,43 +154,53 @@ define <32 x i8> @test_x86_avx2_packuswb
; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
; X86-AVX-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
; X86-AVX-NEXT: ## fixup A - offset: 4, value: LCPI5_0, kind: FK_Data_4
-; X86-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
;
; X86-AVX512VL-LABEL: test_x86_avx2_packuswb_fold:
; X86-AVX512VL: ## %bb.0:
; X86-AVX512VL-NEXT: vmovaps LCPI5_0, %ymm0 ## EVEX TO VEX Compression ymm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
; X86-AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
; X86-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI5_0, kind: FK_Data_4
-; X86-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
;
; X64-AVX-LABEL: test_x86_avx2_packuswb_fold:
; X64-AVX: ## %bb.0:
; X64-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
; X64-AVX-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
; X64-AVX-NEXT: ## fixup A - offset: 4, value: LCPI5_0-4, kind: reloc_riprel_4byte
-; X64-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
;
; X64-AVX512VL-LABEL: test_x86_avx2_packuswb_fold:
; X64-AVX512VL: ## %bb.0:
; X64-AVX512VL-NEXT: vmovaps {{.*}}(%rip), %ymm0 ## EVEX TO VEX Compression ymm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
; X64-AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
; X64-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI5_0-4, kind: reloc_riprel_4byte
-; X64-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> <i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678, i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678>, <16 x i16> zeroinitializer)
ret <32 x i8> %res
}
define <32 x i8> @test_x86_avx2_padds_b(<32 x i8> %a0, <32 x i8> %a1) {
-; AVX2-LABEL: test_x86_avx2_padds_b:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpaddsb %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xec,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_padds_b:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpaddsb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xec,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_padds_b:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpaddsb %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xec,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_padds_b:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpaddsb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xec,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_padds_b:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpaddsb %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xec,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_padds_b:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpaddsb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xec,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.padds.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
@@ -168,15 +208,25 @@ declare <32 x i8> @llvm.x86.avx2.padds.b
define <16 x i16> @test_x86_avx2_padds_w(<16 x i16> %a0, <16 x i16> %a1) {
-; AVX2-LABEL: test_x86_avx2_padds_w:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpaddsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xed,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_padds_w:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpaddsw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xed,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_padds_w:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpaddsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xed,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_padds_w:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpaddsw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xed,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_padds_w:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpaddsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xed,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_padds_w:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpaddsw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xed,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.padds.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -184,15 +234,25 @@ declare <16 x i16> @llvm.x86.avx2.padds.
define <32 x i8> @test_x86_avx2_paddus_b(<32 x i8> %a0, <32 x i8> %a1) {
-; AVX2-LABEL: test_x86_avx2_paddus_b:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpaddusb %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xdc,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_paddus_b:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpaddusb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xdc,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_paddus_b:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpaddusb %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xdc,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_paddus_b:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpaddusb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xdc,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_paddus_b:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpaddusb %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xdc,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_paddus_b:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpaddusb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xdc,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.paddus.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
@@ -200,15 +260,25 @@ declare <32 x i8> @llvm.x86.avx2.paddus.
define <16 x i16> @test_x86_avx2_paddus_w(<16 x i16> %a0, <16 x i16> %a1) {
-; AVX2-LABEL: test_x86_avx2_paddus_w:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpaddusw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xdd,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_paddus_w:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpaddusw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xdd,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_paddus_w:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpaddusw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xdd,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_paddus_w:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpaddusw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xdd,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_paddus_w:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpaddusw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xdd,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_paddus_w:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpaddusw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xdd,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.paddus.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -216,15 +286,25 @@ declare <16 x i16> @llvm.x86.avx2.paddus
define <8 x i32> @test_x86_avx2_pmadd_wd(<16 x i16> %a0, <16 x i16> %a1) {
-; AVX2-LABEL: test_x86_avx2_pmadd_wd:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpmaddwd %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xf5,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_pmadd_wd:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpmaddwd %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf5,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_pmadd_wd:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpmaddwd %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xf5,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_pmadd_wd:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpmaddwd %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf5,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_pmadd_wd:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpmaddwd %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xf5,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_pmadd_wd:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpmaddwd %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf5,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %a0, <16 x i16> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -232,15 +312,25 @@ declare <8 x i32> @llvm.x86.avx2.pmadd.w
define <16 x i16> @test_x86_avx2_pmaxs_w(<16 x i16> %a0, <16 x i16> %a1) {
-; AVX2-LABEL: test_x86_avx2_pmaxs_w:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xee,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_pmaxs_w:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xee,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_pmaxs_w:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xee,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_pmaxs_w:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xee,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_pmaxs_w:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xee,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_pmaxs_w:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xee,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.pmaxs.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -248,15 +338,25 @@ declare <16 x i16> @llvm.x86.avx2.pmaxs.
define <32 x i8> @test_x86_avx2_pmaxu_b(<32 x i8> %a0, <32 x i8> %a1) {
-; AVX2-LABEL: test_x86_avx2_pmaxu_b:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpmaxub %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xde,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_pmaxu_b:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpmaxub %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xde,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_pmaxu_b:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpmaxub %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xde,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_pmaxu_b:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpmaxub %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xde,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_pmaxu_b:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpmaxub %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xde,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_pmaxu_b:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpmaxub %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xde,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.pmaxu.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
@@ -264,15 +364,25 @@ declare <32 x i8> @llvm.x86.avx2.pmaxu.b
define <16 x i16> @test_x86_avx2_pmins_w(<16 x i16> %a0, <16 x i16> %a1) {
-; AVX2-LABEL: test_x86_avx2_pmins_w:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpminsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xea,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_pmins_w:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpminsw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xea,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_pmins_w:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpminsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xea,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_pmins_w:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpminsw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xea,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_pmins_w:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpminsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xea,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_pmins_w:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpminsw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xea,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.pmins.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -280,15 +390,25 @@ declare <16 x i16> @llvm.x86.avx2.pmins.
define <32 x i8> @test_x86_avx2_pminu_b(<32 x i8> %a0, <32 x i8> %a1) {
-; AVX2-LABEL: test_x86_avx2_pminu_b:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpminub %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xda,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_pminu_b:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpminub %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xda,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_pminu_b:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpminub %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xda,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_pminu_b:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpminub %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xda,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_pminu_b:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpminub %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xda,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_pminu_b:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpminub %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xda,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.pminu.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
@@ -296,11 +416,17 @@ declare <32 x i8> @llvm.x86.avx2.pminu.b
define i32 @test_x86_avx2_pmovmskb(<32 x i8> %a0) {
-; CHECK-LABEL: test_x86_avx2_pmovmskb:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmovmskb %ymm0, %eax ## encoding: [0xc5,0xfd,0xd7,0xc0]
-; CHECK-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
-; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_pmovmskb:
+; X86: ## %bb.0:
+; X86-NEXT: vpmovmskb %ymm0, %eax ## encoding: [0xc5,0xfd,0xd7,0xc0]
+; X86-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
+; X86-NEXT: retl ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_pmovmskb:
+; X64: ## %bb.0:
+; X64-NEXT: vpmovmskb %ymm0, %eax ## encoding: [0xc5,0xfd,0xd7,0xc0]
+; X64-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call i32 @llvm.x86.avx2.pmovmskb(<32 x i8> %a0) ; <i32> [#uses=1]
ret i32 %res
}
@@ -308,15 +434,25 @@ declare i32 @llvm.x86.avx2.pmovmskb(<32
define <16 x i16> @test_x86_avx2_pmulh_w(<16 x i16> %a0, <16 x i16> %a1) {
-; AVX2-LABEL: test_x86_avx2_pmulh_w:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpmulhw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xe5,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_pmulh_w:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpmulhw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe5,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_pmulh_w:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpmulhw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xe5,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_pmulh_w:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpmulhw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe5,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_pmulh_w:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpmulhw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xe5,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_pmulh_w:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpmulhw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe5,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -324,47 +460,51 @@ declare <16 x i16> @llvm.x86.avx2.pmulh.
define <16 x i16> @test_x86_avx2_pmulhu_w(<16 x i16> %a0, <16 x i16> %a1) {
-; AVX2-LABEL: test_x86_avx2_pmulhu_w:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpmulhuw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xe4,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_pmulhu_w:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpmulhuw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe4,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_pmulhu_w:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpmulhuw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xe4,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_pmulhu_w:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpmulhuw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe4,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_pmulhu_w:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpmulhuw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xe4,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_pmulhu_w:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpmulhuw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe4,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
declare <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16>, <16 x i16>) nounwind readnone
-define <4 x i64> @test_x86_avx2_pmulu_dq(<8 x i32> %a0, <8 x i32> %a1) {
-; AVX2-LABEL: test_x86_avx2_pmulu_dq:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpmuludq %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xf4,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_pmulu_dq:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpmuludq %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf4,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
- %res = call <4 x i64> @llvm.x86.avx2.pmulu.dq(<8 x i32> %a0, <8 x i32> %a1) ; <<4 x i64>> [#uses=1]
- ret <4 x i64> %res
-}
-declare <4 x i64> @llvm.x86.avx2.pmulu.dq(<8 x i32>, <8 x i32>) nounwind readnone
-
-
define <4 x i64> @test_x86_avx2_psad_bw(<32 x i8> %a0, <32 x i8> %a1) {
-; AVX2-LABEL: test_x86_avx2_psad_bw:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xf6,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_psad_bw:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf6,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_psad_bw:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xf6,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_psad_bw:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf6,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_psad_bw:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xf6,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_psad_bw:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpsadbw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf6,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.psad.bw(<32 x i8> %a0, <32 x i8> %a1) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -372,15 +512,25 @@ declare <4 x i64> @llvm.x86.avx2.psad.bw
define <8 x i32> @test_x86_avx2_psll_d(<8 x i32> %a0, <4 x i32> %a1) {
-; AVX2-LABEL: test_x86_avx2_psll_d:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpslld %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xf2,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_psll_d:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpslld %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf2,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_psll_d:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpslld %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xf2,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_psll_d:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpslld %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf2,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_psll_d:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpslld %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xf2,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_psll_d:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpslld %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf2,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> %a0, <4 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -388,15 +538,25 @@ declare <8 x i32> @llvm.x86.avx2.psll.d(
define <4 x i64> @test_x86_avx2_psll_q(<4 x i64> %a0, <2 x i64> %a1) {
-; AVX2-LABEL: test_x86_avx2_psll_q:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpsllq %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xf3,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_psll_q:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpsllq %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf3,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_psll_q:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpsllq %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xf3,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_psll_q:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpsllq %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf3,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_psll_q:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpsllq %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xf3,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_psll_q:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpsllq %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf3,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> %a0, <2 x i64> %a1) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -404,15 +564,25 @@ declare <4 x i64> @llvm.x86.avx2.psll.q(
define <16 x i16> @test_x86_avx2_psll_w(<16 x i16> %a0, <8 x i16> %a1) {
-; AVX2-LABEL: test_x86_avx2_psll_w:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpsllw %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xf1,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_psll_w:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpsllw %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf1,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_psll_w:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpsllw %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xf1,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_psll_w:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpsllw %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf1,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_psll_w:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpsllw %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xf1,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_psll_w:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpsllw %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf1,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> %a0, <8 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -420,15 +590,25 @@ declare <16 x i16> @llvm.x86.avx2.psll.w
define <8 x i32> @test_x86_avx2_pslli_d(<8 x i32> %a0) {
-; AVX2-LABEL: test_x86_avx2_pslli_d:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpslld $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x72,0xf0,0x07]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_pslli_d:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpslld $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x72,0xf0,0x07]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_pslli_d:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpslld $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x72,0xf0,0x07]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_pslli_d:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpslld $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x72,0xf0,0x07]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_pslli_d:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpslld $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x72,0xf0,0x07]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_pslli_d:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpslld $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x72,0xf0,0x07]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32> %a0, i32 7) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -436,15 +616,25 @@ declare <8 x i32> @llvm.x86.avx2.pslli.d
define <4 x i64> @test_x86_avx2_pslli_q(<4 x i64> %a0) {
-; AVX2-LABEL: test_x86_avx2_pslli_q:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpsllq $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x73,0xf0,0x07]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_pslli_q:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpsllq $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x73,0xf0,0x07]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_pslli_q:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpsllq $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x73,0xf0,0x07]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_pslli_q:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpsllq $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x73,0xf0,0x07]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_pslli_q:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpsllq $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x73,0xf0,0x07]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_pslli_q:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpsllq $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x73,0xf0,0x07]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64> %a0, i32 7) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -452,15 +642,25 @@ declare <4 x i64> @llvm.x86.avx2.pslli.q
define <16 x i16> @test_x86_avx2_pslli_w(<16 x i16> %a0) {
-; AVX2-LABEL: test_x86_avx2_pslli_w:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpsllw $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x71,0xf0,0x07]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_pslli_w:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpsllw $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x71,0xf0,0x07]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_pslli_w:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpsllw $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x71,0xf0,0x07]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_pslli_w:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpsllw $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x71,0xf0,0x07]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_pslli_w:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpsllw $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x71,0xf0,0x07]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_pslli_w:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpsllw $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x71,0xf0,0x07]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16> %a0, i32 7) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -468,15 +668,25 @@ declare <16 x i16> @llvm.x86.avx2.pslli.
define <8 x i32> @test_x86_avx2_psra_d(<8 x i32> %a0, <4 x i32> %a1) {
-; AVX2-LABEL: test_x86_avx2_psra_d:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpsrad %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xe2,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_psra_d:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpsrad %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe2,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_psra_d:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpsrad %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xe2,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_psra_d:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpsrad %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe2,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_psra_d:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpsrad %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xe2,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_psra_d:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpsrad %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe2,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> %a0, <4 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -484,15 +694,25 @@ declare <8 x i32> @llvm.x86.avx2.psra.d(
define <16 x i16> @test_x86_avx2_psra_w(<16 x i16> %a0, <8 x i16> %a1) {
-; AVX2-LABEL: test_x86_avx2_psra_w:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpsraw %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xe1,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_psra_w:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpsraw %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe1,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_psra_w:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpsraw %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xe1,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_psra_w:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpsraw %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe1,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_psra_w:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpsraw %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xe1,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_psra_w:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpsraw %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe1,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> %a0, <8 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -500,15 +720,25 @@ declare <16 x i16> @llvm.x86.avx2.psra.w
define <8 x i32> @test_x86_avx2_psrai_d(<8 x i32> %a0) {
-; AVX2-LABEL: test_x86_avx2_psrai_d:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpsrad $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x72,0xe0,0x07]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_psrai_d:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpsrad $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x72,0xe0,0x07]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_psrai_d:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpsrad $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x72,0xe0,0x07]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_psrai_d:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpsrad $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x72,0xe0,0x07]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_psrai_d:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpsrad $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x72,0xe0,0x07]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_psrai_d:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpsrad $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x72,0xe0,0x07]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32> %a0, i32 7) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -516,15 +746,25 @@ declare <8 x i32> @llvm.x86.avx2.psrai.d
define <16 x i16> @test_x86_avx2_psrai_w(<16 x i16> %a0) {
-; AVX2-LABEL: test_x86_avx2_psrai_w:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpsraw $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x71,0xe0,0x07]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_psrai_w:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpsraw $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x71,0xe0,0x07]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_psrai_w:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpsraw $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x71,0xe0,0x07]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_psrai_w:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpsraw $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x71,0xe0,0x07]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_psrai_w:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpsraw $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x71,0xe0,0x07]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_psrai_w:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpsraw $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x71,0xe0,0x07]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16> %a0, i32 7) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -532,15 +772,25 @@ declare <16 x i16> @llvm.x86.avx2.psrai.
define <8 x i32> @test_x86_avx2_psrl_d(<8 x i32> %a0, <4 x i32> %a1) {
-; AVX2-LABEL: test_x86_avx2_psrl_d:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpsrld %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xd2,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_psrl_d:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpsrld %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xd2,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_psrl_d:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpsrld %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xd2,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_psrl_d:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpsrld %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xd2,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_psrl_d:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpsrld %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xd2,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_psrl_d:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpsrld %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xd2,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> %a0, <4 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -548,15 +798,25 @@ declare <8 x i32> @llvm.x86.avx2.psrl.d(
define <4 x i64> @test_x86_avx2_psrl_q(<4 x i64> %a0, <2 x i64> %a1) {
-; AVX2-LABEL: test_x86_avx2_psrl_q:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpsrlq %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xd3,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_psrl_q:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpsrlq %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xd3,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_psrl_q:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpsrlq %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xd3,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_psrl_q:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpsrlq %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xd3,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_psrl_q:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpsrlq %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xd3,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_psrl_q:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpsrlq %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xd3,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> %a0, <2 x i64> %a1) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -564,15 +824,25 @@ declare <4 x i64> @llvm.x86.avx2.psrl.q(
define <16 x i16> @test_x86_avx2_psrl_w(<16 x i16> %a0, <8 x i16> %a1) {
-; AVX2-LABEL: test_x86_avx2_psrl_w:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpsrlw %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xd1,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_psrl_w:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpsrlw %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xd1,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_psrl_w:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpsrlw %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xd1,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_psrl_w:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpsrlw %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xd1,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_psrl_w:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpsrlw %xmm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xd1,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_psrl_w:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpsrlw %xmm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xd1,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> %a0, <8 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -580,15 +850,25 @@ declare <16 x i16> @llvm.x86.avx2.psrl.w
define <8 x i32> @test_x86_avx2_psrli_d(<8 x i32> %a0) {
-; AVX2-LABEL: test_x86_avx2_psrli_d:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpsrld $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x72,0xd0,0x07]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_psrli_d:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpsrld $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x72,0xd0,0x07]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_psrli_d:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpsrld $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x72,0xd0,0x07]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_psrli_d:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpsrld $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x72,0xd0,0x07]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_psrli_d:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpsrld $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x72,0xd0,0x07]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_psrli_d:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpsrld $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x72,0xd0,0x07]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.psrli.d(<8 x i32> %a0, i32 7) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -596,15 +876,25 @@ declare <8 x i32> @llvm.x86.avx2.psrli.d
define <4 x i64> @test_x86_avx2_psrli_q(<4 x i64> %a0) {
-; AVX2-LABEL: test_x86_avx2_psrli_q:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpsrlq $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x73,0xd0,0x07]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_psrli_q:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpsrlq $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x73,0xd0,0x07]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_psrli_q:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpsrlq $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x73,0xd0,0x07]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_psrli_q:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpsrlq $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x73,0xd0,0x07]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_psrli_q:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpsrlq $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x73,0xd0,0x07]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_psrli_q:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpsrlq $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x73,0xd0,0x07]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.psrli.q(<4 x i64> %a0, i32 7) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -612,15 +902,25 @@ declare <4 x i64> @llvm.x86.avx2.psrli.q
define <16 x i16> @test_x86_avx2_psrli_w(<16 x i16> %a0) {
-; AVX2-LABEL: test_x86_avx2_psrli_w:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpsrlw $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x71,0xd0,0x07]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_psrli_w:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpsrlw $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x71,0xd0,0x07]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_psrli_w:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpsrlw $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x71,0xd0,0x07]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_psrli_w:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpsrlw $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x71,0xd0,0x07]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_psrli_w:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpsrlw $7, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x71,0xd0,0x07]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_psrli_w:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpsrlw $7, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x71,0xd0,0x07]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.psrli.w(<16 x i16> %a0, i32 7) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -628,15 +928,25 @@ declare <16 x i16> @llvm.x86.avx2.psrli.
define <32 x i8> @test_x86_avx2_psubs_b(<32 x i8> %a0, <32 x i8> %a1) {
-; AVX2-LABEL: test_x86_avx2_psubs_b:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpsubsb %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xe8,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_psubs_b:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpsubsb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe8,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_psubs_b:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpsubsb %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xe8,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_psubs_b:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpsubsb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe8,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_psubs_b:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpsubsb %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xe8,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_psubs_b:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpsubsb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe8,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.psubs.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
@@ -644,15 +954,25 @@ declare <32 x i8> @llvm.x86.avx2.psubs.b
define <16 x i16> @test_x86_avx2_psubs_w(<16 x i16> %a0, <16 x i16> %a1) {
-; AVX2-LABEL: test_x86_avx2_psubs_w:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpsubsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xe9,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_psubs_w:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpsubsw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe9,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_psubs_w:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpsubsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xe9,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_psubs_w:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpsubsw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe9,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_psubs_w:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpsubsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xe9,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_psubs_w:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpsubsw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe9,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.psubs.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -660,15 +980,25 @@ declare <16 x i16> @llvm.x86.avx2.psubs.
define <32 x i8> @test_x86_avx2_psubus_b(<32 x i8> %a0, <32 x i8> %a1) {
-; AVX2-LABEL: test_x86_avx2_psubus_b:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpsubusb %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xd8,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_psubus_b:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpsubusb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xd8,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_psubus_b:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpsubusb %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xd8,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_psubus_b:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpsubusb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xd8,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_psubus_b:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpsubusb %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xd8,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_psubus_b:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpsubusb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xd8,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.psubus.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
@@ -676,25 +1006,40 @@ declare <32 x i8> @llvm.x86.avx2.psubus.
define <16 x i16> @test_x86_avx2_psubus_w(<16 x i16> %a0, <16 x i16> %a1) {
-; AVX2-LABEL: test_x86_avx2_psubus_w:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpsubusw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xd9,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_psubus_w:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpsubusw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xd9,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_psubus_w:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpsubusw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xd9,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_psubus_w:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpsubusw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xd9,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_psubus_w:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpsubusw %ymm1, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0xd9,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_psubus_w:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpsubusw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xd9,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.psubus.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
declare <16 x i16> @llvm.x86.avx2.psubus.w(<16 x i16>, <16 x i16>) nounwind readnone
define <8 x i32> @test_x86_avx2_phadd_d(<8 x i32> %a0, <8 x i32> %a1) {
-; CHECK-LABEL: test_x86_avx2_phadd_d:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vphaddd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x02,0xc1]
-; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_phadd_d:
+; X86: ## %bb.0:
+; X86-NEXT: vphaddd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x02,0xc1]
+; X86-NEXT: retl ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_phadd_d:
+; X64: ## %bb.0:
+; X64-NEXT: vphaddd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x02,0xc1]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.phadd.d(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -702,10 +1047,15 @@ declare <8 x i32> @llvm.x86.avx2.phadd.d
define <16 x i16> @test_x86_avx2_phadd_sw(<16 x i16> %a0, <16 x i16> %a1) {
-; CHECK-LABEL: test_x86_avx2_phadd_sw:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vphaddsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x03,0xc1]
-; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_phadd_sw:
+; X86: ## %bb.0:
+; X86-NEXT: vphaddsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x03,0xc1]
+; X86-NEXT: retl ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_phadd_sw:
+; X64: ## %bb.0:
+; X64-NEXT: vphaddsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x03,0xc1]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.phadd.sw(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -713,10 +1063,15 @@ declare <16 x i16> @llvm.x86.avx2.phadd.
define <16 x i16> @test_x86_avx2_phadd_w(<16 x i16> %a0, <16 x i16> %a1) {
-; CHECK-LABEL: test_x86_avx2_phadd_w:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vphaddw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x01,0xc1]
-; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_phadd_w:
+; X86: ## %bb.0:
+; X86-NEXT: vphaddw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x01,0xc1]
+; X86-NEXT: retl ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_phadd_w:
+; X64: ## %bb.0:
+; X64-NEXT: vphaddw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x01,0xc1]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.phadd.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -724,10 +1079,15 @@ declare <16 x i16> @llvm.x86.avx2.phadd.
define <8 x i32> @test_x86_avx2_phsub_d(<8 x i32> %a0, <8 x i32> %a1) {
-; CHECK-LABEL: test_x86_avx2_phsub_d:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vphsubd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x06,0xc1]
-; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_phsub_d:
+; X86: ## %bb.0:
+; X86-NEXT: vphsubd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x06,0xc1]
+; X86-NEXT: retl ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_phsub_d:
+; X64: ## %bb.0:
+; X64-NEXT: vphsubd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x06,0xc1]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.phsub.d(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -735,10 +1095,15 @@ declare <8 x i32> @llvm.x86.avx2.phsub.d
define <16 x i16> @test_x86_avx2_phsub_sw(<16 x i16> %a0, <16 x i16> %a1) {
-; CHECK-LABEL: test_x86_avx2_phsub_sw:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vphsubsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x07,0xc1]
-; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_phsub_sw:
+; X86: ## %bb.0:
+; X86-NEXT: vphsubsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x07,0xc1]
+; X86-NEXT: retl ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_phsub_sw:
+; X64: ## %bb.0:
+; X64-NEXT: vphsubsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x07,0xc1]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.phsub.sw(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -746,10 +1111,15 @@ declare <16 x i16> @llvm.x86.avx2.phsub.
define <16 x i16> @test_x86_avx2_phsub_w(<16 x i16> %a0, <16 x i16> %a1) {
-; CHECK-LABEL: test_x86_avx2_phsub_w:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vphsubw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x05,0xc1]
-; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_phsub_w:
+; X86: ## %bb.0:
+; X86-NEXT: vphsubw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x05,0xc1]
+; X86-NEXT: retl ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_phsub_w:
+; X64: ## %bb.0:
+; X64-NEXT: vphsubw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x05,0xc1]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.phsub.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -757,15 +1127,25 @@ declare <16 x i16> @llvm.x86.avx2.phsub.
define <16 x i16> @test_x86_avx2_pmadd_ub_sw(<32 x i8> %a0, <32 x i8> %a1) {
-; AVX2-LABEL: test_x86_avx2_pmadd_ub_sw:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpmaddubsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x04,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_pmadd_ub_sw:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpmaddubsw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x04,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_pmadd_ub_sw:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpmaddubsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x04,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_pmadd_ub_sw:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpmaddubsw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x04,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_pmadd_ub_sw:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpmaddubsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x04,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_pmadd_ub_sw:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpmaddubsw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x04,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.pmadd.ub.sw(<32 x i8> %a0, <32 x i8> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -778,41 +1158,51 @@ define <16 x i16> @test_x86_avx2_pmadd_u
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-AVX-NEXT: vmovdqa (%eax), %ymm1 ## encoding: [0xc5,0xfd,0x6f,0x08]
; X86-AVX-NEXT: vpmaddubsw %ymm0, %ymm1, %ymm0 ## encoding: [0xc4,0xe2,0x75,0x04,0xc0]
-; X86-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
;
; X86-AVX512VL-LABEL: test_x86_avx2_pmadd_ub_sw_load_op0:
; X86-AVX512VL: ## %bb.0:
; X86-AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-AVX512VL-NEXT: vmovdqa (%eax), %ymm1 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0x08]
; X86-AVX512VL-NEXT: vpmaddubsw %ymm0, %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x04,0xc0]
-; X86-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
;
; X64-AVX-LABEL: test_x86_avx2_pmadd_ub_sw_load_op0:
; X64-AVX: ## %bb.0:
; X64-AVX-NEXT: vmovdqa (%rdi), %ymm1 ## encoding: [0xc5,0xfd,0x6f,0x0f]
; X64-AVX-NEXT: vpmaddubsw %ymm0, %ymm1, %ymm0 ## encoding: [0xc4,0xe2,0x75,0x04,0xc0]
-; X64-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
;
; X64-AVX512VL-LABEL: test_x86_avx2_pmadd_ub_sw_load_op0:
; X64-AVX512VL: ## %bb.0:
; X64-AVX512VL-NEXT: vmovdqa (%rdi), %ymm1 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0x0f]
; X64-AVX512VL-NEXT: vpmaddubsw %ymm0, %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x04,0xc0]
-; X64-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%a0 = load <32 x i8>, <32 x i8>* %ptr
%res = call <16 x i16> @llvm.x86.avx2.pmadd.ub.sw(<32 x i8> %a0, <32 x i8> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
define <16 x i16> @test_x86_avx2_pmul_hr_sw(<16 x i16> %a0, <16 x i16> %a1) {
-; AVX2-LABEL: test_x86_avx2_pmul_hr_sw:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpmulhrsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x0b,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_pmul_hr_sw:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpmulhrsw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x0b,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_pmul_hr_sw:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpmulhrsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x0b,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_pmul_hr_sw:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpmulhrsw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x0b,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_pmul_hr_sw:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpmulhrsw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x0b,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_pmul_hr_sw:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpmulhrsw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x0b,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.pmul.hr.sw(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -820,15 +1210,25 @@ declare <16 x i16> @llvm.x86.avx2.pmul.h
define <32 x i8> @test_x86_avx2_pshuf_b(<32 x i8> %a0, <32 x i8> %a1) {
-; AVX2-LABEL: test_x86_avx2_pshuf_b:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpshufb %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x00,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_pshuf_b:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpshufb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x00,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_pshuf_b:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpshufb %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x00,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_pshuf_b:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpshufb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x00,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_pshuf_b:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpshufb %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x00,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_pshuf_b:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpshufb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x00,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %a0, <32 x i8> %a1) ; <<16 x i8>> [#uses=1]
ret <32 x i8> %res
}
@@ -836,10 +1236,15 @@ declare <32 x i8> @llvm.x86.avx2.pshuf.b
define <32 x i8> @test_x86_avx2_psign_b(<32 x i8> %a0, <32 x i8> %a1) {
-; CHECK-LABEL: test_x86_avx2_psign_b:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpsignb %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x08,0xc1]
-; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_psign_b:
+; X86: ## %bb.0:
+; X86-NEXT: vpsignb %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x08,0xc1]
+; X86-NEXT: retl ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_psign_b:
+; X64: ## %bb.0:
+; X64-NEXT: vpsignb %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x08,0xc1]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.psign.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
@@ -847,10 +1252,15 @@ declare <32 x i8> @llvm.x86.avx2.psign.b
define <8 x i32> @test_x86_avx2_psign_d(<8 x i32> %a0, <8 x i32> %a1) {
-; CHECK-LABEL: test_x86_avx2_psign_d:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpsignd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x0a,0xc1]
-; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_psign_d:
+; X86: ## %bb.0:
+; X86-NEXT: vpsignd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x0a,0xc1]
+; X86-NEXT: retl ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_psign_d:
+; X64: ## %bb.0:
+; X64-NEXT: vpsignd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x0a,0xc1]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.psign.d(<8 x i32> %a0, <8 x i32> %a1) ; <<4 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -858,10 +1268,15 @@ declare <8 x i32> @llvm.x86.avx2.psign.d
define <16 x i16> @test_x86_avx2_psign_w(<16 x i16> %a0, <16 x i16> %a1) {
-; CHECK-LABEL: test_x86_avx2_psign_w:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpsignw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x09,0xc1]
-; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_psign_w:
+; X86: ## %bb.0:
+; X86-NEXT: vpsignw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x09,0xc1]
+; X86-NEXT: retl ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_psign_w:
+; X64: ## %bb.0:
+; X64-NEXT: vpsignw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x09,0xc1]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.psign.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -869,10 +1284,15 @@ declare <16 x i16> @llvm.x86.avx2.psign.
define <16 x i16> @test_x86_avx2_mpsadbw(<32 x i8> %a0, <32 x i8> %a1) {
-; CHECK-LABEL: test_x86_avx2_mpsadbw:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vmpsadbw $7, %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe3,0x7d,0x42,0xc1,0x07]
-; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_mpsadbw:
+; X86: ## %bb.0:
+; X86-NEXT: vmpsadbw $7, %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe3,0x7d,0x42,0xc1,0x07]
+; X86-NEXT: retl ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_mpsadbw:
+; X64: ## %bb.0:
+; X64-NEXT: vmpsadbw $7, %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe3,0x7d,0x42,0xc1,0x07]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.mpsadbw(<32 x i8> %a0, <32 x i8> %a1, i8 7) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -880,15 +1300,25 @@ declare <16 x i16> @llvm.x86.avx2.mpsadb
define <16 x i16> @test_x86_avx2_packusdw(<8 x i32> %a0, <8 x i32> %a1) {
-; AVX2-LABEL: test_x86_avx2_packusdw:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpackusdw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x2b,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_packusdw:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpackusdw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x2b,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_packusdw:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpackusdw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x2b,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_packusdw:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpackusdw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x2b,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_packusdw:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpackusdw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x2b,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_packusdw:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpackusdw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x2b,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> %a0, <8 x i32> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -900,39 +1330,44 @@ define <16 x i16> @test_x86_avx2_packusd
; X86-AVX: ## %bb.0:
; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0]
; X86-AVX-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; X86-AVX-NEXT: ## fixup A - offset: 4, value: LCPI55_0, kind: FK_Data_4
-; X86-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-NEXT: ## fixup A - offset: 4, value: LCPI54_0, kind: FK_Data_4
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
;
; X86-AVX512VL-LABEL: test_x86_avx2_packusdw_fold:
; X86-AVX512VL: ## %bb.0:
-; X86-AVX512VL-NEXT: vmovaps LCPI55_0, %ymm0 ## EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0]
+; X86-AVX512VL-NEXT: vmovaps LCPI54_0, %ymm0 ## EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0]
; X86-AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; X86-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI55_0, kind: FK_Data_4
-; X86-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI54_0, kind: FK_Data_4
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
;
; X64-AVX-LABEL: test_x86_avx2_packusdw_fold:
; X64-AVX: ## %bb.0:
; X64-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0]
; X64-AVX-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; X64-AVX-NEXT: ## fixup A - offset: 4, value: LCPI55_0-4, kind: reloc_riprel_4byte
-; X64-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-AVX-NEXT: ## fixup A - offset: 4, value: LCPI54_0-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
;
; X64-AVX512VL-LABEL: test_x86_avx2_packusdw_fold:
; X64-AVX512VL: ## %bb.0:
; X64-AVX512VL-NEXT: vmovaps {{.*}}(%rip), %ymm0 ## EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0]
; X64-AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
-; X64-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI55_0-4, kind: reloc_riprel_4byte
-; X64-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI54_0-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> zeroinitializer, <8 x i32> <i32 255, i32 32767, i32 65535, i32 -1, i32 -32767, i32 -65535, i32 0, i32 -256>)
ret <16 x i16> %res
}
define <32 x i8> @test_x86_avx2_pblendvb(<32 x i8> %a0, <32 x i8> %a1, <32 x i8> %a2) {
-; CHECK-LABEL: test_x86_avx2_pblendvb:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpblendvb %ymm2, %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe3,0x7d,0x4c,0xc1,0x20]
-; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_pblendvb:
+; X86: ## %bb.0:
+; X86-NEXT: vpblendvb %ymm2, %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe3,0x7d,0x4c,0xc1,0x20]
+; X86-NEXT: retl ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_pblendvb:
+; X64: ## %bb.0:
+; X64-NEXT: vpblendvb %ymm2, %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe3,0x7d,0x4c,0xc1,0x20]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8> %a0, <32 x i8> %a1, <32 x i8> %a2) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
@@ -940,11 +1375,17 @@ declare <32 x i8> @llvm.x86.avx2.pblendv
define <16 x i16> @test_x86_avx2_pblendw(<16 x i16> %a0, <16 x i16> %a1) {
-; CHECK-LABEL: test_x86_avx2_pblendw:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpblendw $7, %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe3,0x7d,0x0e,0xc1,0x07]
-; CHECK-NEXT: ## ymm0 = ymm1[0,1,2],ymm0[3,4,5,6,7],ymm1[8,9,10],ymm0[11,12,13,14,15]
-; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_pblendw:
+; X86: ## %bb.0:
+; X86-NEXT: vpblendw $7, %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe3,0x7d,0x0e,0xc1,0x07]
+; X86-NEXT: ## ymm0 = ymm1[0,1,2],ymm0[3,4,5,6,7],ymm1[8,9,10],ymm0[11,12,13,14,15]
+; X86-NEXT: retl ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_pblendw:
+; X64: ## %bb.0:
+; X64-NEXT: vpblendw $7, %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe3,0x7d,0x0e,0xc1,0x07]
+; X64-NEXT: ## ymm0 = ymm1[0,1,2],ymm0[3,4,5,6,7],ymm1[8,9,10],ymm0[11,12,13,14,15]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16> %a0, <16 x i16> %a1, i8 7) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -952,15 +1393,25 @@ declare <16 x i16> @llvm.x86.avx2.pblend
define <32 x i8> @test_x86_avx2_pmaxsb(<32 x i8> %a0, <32 x i8> %a1) {
-; AVX2-LABEL: test_x86_avx2_pmaxsb:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x3c,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_pmaxsb:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x3c,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_pmaxsb:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x3c,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_pmaxsb:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x3c,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_pmaxsb:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x3c,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_pmaxsb:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x3c,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.pmaxs.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
@@ -968,15 +1419,25 @@ declare <32 x i8> @llvm.x86.avx2.pmaxs.b
define <8 x i32> @test_x86_avx2_pmaxsd(<8 x i32> %a0, <8 x i32> %a1) {
-; AVX2-LABEL: test_x86_avx2_pmaxsd:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x3d,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_pmaxsd:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x3d,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_pmaxsd:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x3d,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_pmaxsd:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x3d,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_pmaxsd:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x3d,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_pmaxsd:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x3d,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.pmaxs.d(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -984,15 +1445,25 @@ declare <8 x i32> @llvm.x86.avx2.pmaxs.d
define <8 x i32> @test_x86_avx2_pmaxud(<8 x i32> %a0, <8 x i32> %a1) {
-; AVX2-LABEL: test_x86_avx2_pmaxud:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x3f,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_pmaxud:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpmaxud %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x3f,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_pmaxud:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpmaxud %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x3f,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_pmaxud:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpmaxud %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x3f,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_pmaxud:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpmaxud %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x3f,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_pmaxud:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpmaxud %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x3f,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.pmaxu.d(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -1000,15 +1471,25 @@ declare <8 x i32> @llvm.x86.avx2.pmaxu.d
define <16 x i16> @test_x86_avx2_pmaxuw(<16 x i16> %a0, <16 x i16> %a1) {
-; AVX2-LABEL: test_x86_avx2_pmaxuw:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x3e,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_pmaxuw:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x3e,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_pmaxuw:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x3e,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_pmaxuw:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x3e,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_pmaxuw:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x3e,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_pmaxuw:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x3e,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.pmaxu.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
@@ -1016,15 +1497,25 @@ declare <16 x i16> @llvm.x86.avx2.pmaxu.
define <32 x i8> @test_x86_avx2_pminsb(<32 x i8> %a0, <32 x i8> %a1) {
-; AVX2-LABEL: test_x86_avx2_pminsb:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpminsb %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x38,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_pminsb:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpminsb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x38,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_pminsb:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpminsb %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x38,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_pminsb:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpminsb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x38,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_pminsb:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpminsb %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x38,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_pminsb:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpminsb %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x38,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.pmins.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1]
ret <32 x i8> %res
}
@@ -1032,15 +1523,25 @@ declare <32 x i8> @llvm.x86.avx2.pmins.b
define <8 x i32> @test_x86_avx2_pminsd(<8 x i32> %a0, <8 x i32> %a1) {
-; AVX2-LABEL: test_x86_avx2_pminsd:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x39,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_pminsd:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpminsd %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x39,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_pminsd:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpminsd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x39,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_pminsd:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpminsd %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x39,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_pminsd:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpminsd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x39,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_pminsd:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpminsd %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x39,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.pmins.d(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -1048,15 +1549,25 @@ declare <8 x i32> @llvm.x86.avx2.pmins.d
define <8 x i32> @test_x86_avx2_pminud(<8 x i32> %a0, <8 x i32> %a1) {
-; AVX2-LABEL: test_x86_avx2_pminud:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x3b,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_pminud:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpminud %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x3b,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_pminud:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpminud %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x3b,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_pminud:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpminud %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x3b,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_pminud:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpminud %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x3b,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_pminud:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpminud %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x3b,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.pminu.d(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -1064,34 +1575,43 @@ declare <8 x i32> @llvm.x86.avx2.pminu.d
define <16 x i16> @test_x86_avx2_pminuw(<16 x i16> %a0, <16 x i16> %a1) {
-; AVX2-LABEL: test_x86_avx2_pminuw:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpminuw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x3a,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_pminuw:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpminuw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x3a,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_pminuw:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpminuw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x3a,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_pminuw:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpminuw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x3a,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_pminuw:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpminuw %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x3a,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_pminuw:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpminuw %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x3a,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.pminu.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1]
ret <16 x i16> %res
}
declare <16 x i16> @llvm.x86.avx2.pminu.w(<16 x i16>, <16 x i16>) nounwind readnone
-define <4 x i64> @test_x86_avx2_pmul.dq(<8 x i32> %a0, <8 x i32> %a1) {
- %res = call <4 x i64> @llvm.x86.avx2.pmul.dq(<8 x i32> %a0, <8 x i32> %a1) ; <<2 x i64>> [#uses=1]
- ret <4 x i64> %res
-}
-declare <4 x i64> @llvm.x86.avx2.pmul.dq(<8 x i32>, <8 x i32>) nounwind readnone
-
-
define <4 x i32> @test_x86_avx2_pblendd_128(<4 x i32> %a0, <4 x i32> %a1) {
-; CHECK-LABEL: test_x86_avx2_pblendd_128:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vblendps $8, %xmm0, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x71,0x0c,0xc0,0x08]
-; CHECK-NEXT: ## xmm0 = xmm1[0,1,2],xmm0[3]
-; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_pblendd_128:
+; X86: ## %bb.0:
+; X86-NEXT: vblendps $8, %xmm0, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x71,0x0c,0xc0,0x08]
+; X86-NEXT: ## xmm0 = xmm1[0,1,2],xmm0[3]
+; X86-NEXT: retl ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_pblendd_128:
+; X64: ## %bb.0:
+; X64-NEXT: vblendps $8, %xmm0, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x71,0x0c,0xc0,0x08]
+; X64-NEXT: ## xmm0 = xmm1[0,1,2],xmm0[3]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32> %a0, <4 x i32> %a1, i8 7) ; <<4 x i32>> [#uses=1]
ret <4 x i32> %res
}
@@ -1099,11 +1619,17 @@ declare <4 x i32> @llvm.x86.avx2.pblendd
define <8 x i32> @test_x86_avx2_pblendd_256(<8 x i32> %a0, <8 x i32> %a1) {
-; CHECK-LABEL: test_x86_avx2_pblendd_256:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vblendps $7, %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe3,0x7d,0x0c,0xc1,0x07]
-; CHECK-NEXT: ## ymm0 = ymm1[0,1,2],ymm0[3,4,5,6,7]
-; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-LABEL: test_x86_avx2_pblendd_256:
+; X86: ## %bb.0:
+; X86-NEXT: vblendps $7, %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe3,0x7d,0x0c,0xc1,0x07]
+; X86-NEXT: ## ymm0 = ymm1[0,1,2],ymm0[3,4,5,6,7]
+; X86-NEXT: retl ## encoding: [0xc3]
+;
+; X64-LABEL: test_x86_avx2_pblendd_256:
+; X64: ## %bb.0:
+; X64-NEXT: vblendps $7, %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe3,0x7d,0x0c,0xc1,0x07]
+; X64-NEXT: ## ymm0 = ymm1[0,1,2],ymm0[3,4,5,6,7]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32> %a0, <8 x i32> %a1, i8 7) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -1114,15 +1640,25 @@ declare <8 x i32> @llvm.x86.avx2.pblendd
; and its lowering. Indeed, the offsets are the first source in
; the instruction.
define <8 x i32> @test_x86_avx2_permd(<8 x i32> %a0, <8 x i32> %a1) {
-; AVX2-LABEL: test_x86_avx2_permd:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0 ## encoding: [0xc4,0xe2,0x75,0x16,0xc0]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_permd:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x16,0xc0]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_permd:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpermps %ymm0, %ymm1, %ymm0 ## encoding: [0xc4,0xe2,0x75,0x16,0xc0]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_permd:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x16,0xc0]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_permd:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpermps %ymm0, %ymm1, %ymm0 ## encoding: [0xc4,0xe2,0x75,0x16,0xc0]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_permd:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x16,0xc0]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -1133,15 +1669,25 @@ declare <8 x i32> @llvm.x86.avx2.permd(<
; and its lowering. Indeed, the offsets are the first source in
; the instruction.
define <8 x float> @test_x86_avx2_permps(<8 x float> %a0, <8 x i32> %a1) {
-; AVX2-LABEL: test_x86_avx2_permps:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0 ## encoding: [0xc4,0xe2,0x75,0x16,0xc0]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_permps:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x16,0xc0]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_permps:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpermps %ymm0, %ymm1, %ymm0 ## encoding: [0xc4,0xe2,0x75,0x16,0xc0]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_permps:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x16,0xc0]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_permps:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpermps %ymm0, %ymm1, %ymm0 ## encoding: [0xc4,0xe2,0x75,0x16,0xc0]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_permps:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x16,0xc0]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <8 x float> @llvm.x86.avx2.permps(<8 x float> %a0, <8 x i32> %a1) ; <<8 x float>> [#uses=1]
ret <8 x float> %res
}
@@ -1153,12 +1699,12 @@ define <2 x i64> @test_x86_avx2_maskload
; X86: ## %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-NEXT: vpmaskmovq (%eax), %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0xf9,0x8c,0x00]
-; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-NEXT: retl ## encoding: [0xc3]
;
; X64-LABEL: test_x86_avx2_maskload_q:
; X64: ## %bb.0:
; X64-NEXT: vpmaskmovq (%rdi), %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0xf9,0x8c,0x07]
-; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <2 x i64> @llvm.x86.avx2.maskload.q(i8* %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]
ret <2 x i64> %res
}
@@ -1170,12 +1716,12 @@ define <4 x i64> @test_x86_avx2_maskload
; X86: ## %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-NEXT: vpmaskmovq (%eax), %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0xfd,0x8c,0x00]
-; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-NEXT: retl ## encoding: [0xc3]
;
; X64-LABEL: test_x86_avx2_maskload_q_256:
; X64: ## %bb.0:
; X64-NEXT: vpmaskmovq (%rdi), %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0xfd,0x8c,0x07]
-; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.maskload.q.256(i8* %a0, <4 x i64> %a1) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -1187,12 +1733,12 @@ define <4 x i32> @test_x86_avx2_maskload
; X86: ## %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-NEXT: vpmaskmovd (%eax), %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x8c,0x00]
-; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-NEXT: retl ## encoding: [0xc3]
;
; X64-LABEL: test_x86_avx2_maskload_d:
; X64: ## %bb.0:
; X64-NEXT: vpmaskmovd (%rdi), %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x8c,0x07]
-; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <4 x i32> @llvm.x86.avx2.maskload.d(i8* %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
ret <4 x i32> %res
}
@@ -1204,12 +1750,12 @@ define <8 x i32> @test_x86_avx2_maskload
; X86: ## %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-NEXT: vpmaskmovd (%eax), %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x8c,0x00]
-; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-NEXT: retl ## encoding: [0xc3]
;
; X64-LABEL: test_x86_avx2_maskload_d_256:
; X64: ## %bb.0:
; X64-NEXT: vpmaskmovd (%rdi), %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x8c,0x07]
-; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.maskload.d.256(i8* %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -1221,12 +1767,12 @@ define void @test_x86_avx2_maskstore_q(i
; X86: ## %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-NEXT: vpmaskmovq %xmm1, %xmm0, (%eax) ## encoding: [0xc4,0xe2,0xf9,0x8e,0x08]
-; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-NEXT: retl ## encoding: [0xc3]
;
; X64-LABEL: test_x86_avx2_maskstore_q:
; X64: ## %bb.0:
; X64-NEXT: vpmaskmovq %xmm1, %xmm0, (%rdi) ## encoding: [0xc4,0xe2,0xf9,0x8e,0x0f]
-; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-NEXT: retq ## encoding: [0xc3]
call void @llvm.x86.avx2.maskstore.q(i8* %a0, <2 x i64> %a1, <2 x i64> %a2)
ret void
}
@@ -1239,13 +1785,13 @@ define void @test_x86_avx2_maskstore_q_2
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-NEXT: vpmaskmovq %ymm1, %ymm0, (%eax) ## encoding: [0xc4,0xe2,0xfd,0x8e,0x08]
; X86-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
-; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-NEXT: retl ## encoding: [0xc3]
;
; X64-LABEL: test_x86_avx2_maskstore_q_256:
; X64: ## %bb.0:
; X64-NEXT: vpmaskmovq %ymm1, %ymm0, (%rdi) ## encoding: [0xc4,0xe2,0xfd,0x8e,0x0f]
; X64-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
-; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-NEXT: retq ## encoding: [0xc3]
call void @llvm.x86.avx2.maskstore.q.256(i8* %a0, <4 x i64> %a1, <4 x i64> %a2)
ret void
}
@@ -1257,12 +1803,12 @@ define void @test_x86_avx2_maskstore_d(i
; X86: ## %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-NEXT: vpmaskmovd %xmm1, %xmm0, (%eax) ## encoding: [0xc4,0xe2,0x79,0x8e,0x08]
-; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-NEXT: retl ## encoding: [0xc3]
;
; X64-LABEL: test_x86_avx2_maskstore_d:
; X64: ## %bb.0:
; X64-NEXT: vpmaskmovd %xmm1, %xmm0, (%rdi) ## encoding: [0xc4,0xe2,0x79,0x8e,0x0f]
-; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-NEXT: retq ## encoding: [0xc3]
call void @llvm.x86.avx2.maskstore.d(i8* %a0, <4 x i32> %a1, <4 x i32> %a2)
ret void
}
@@ -1275,13 +1821,13 @@ define void @test_x86_avx2_maskstore_d_2
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-NEXT: vpmaskmovd %ymm1, %ymm0, (%eax) ## encoding: [0xc4,0xe2,0x7d,0x8e,0x08]
; X86-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
-; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-NEXT: retl ## encoding: [0xc3]
;
; X64-LABEL: test_x86_avx2_maskstore_d_256:
; X64: ## %bb.0:
; X64-NEXT: vpmaskmovd %ymm1, %ymm0, (%rdi) ## encoding: [0xc4,0xe2,0x7d,0x8e,0x0f]
; X64-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
-; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-NEXT: retq ## encoding: [0xc3]
call void @llvm.x86.avx2.maskstore.d.256(i8* %a0, <8 x i32> %a1, <8 x i32> %a2)
ret void
}
@@ -1289,15 +1835,25 @@ declare void @llvm.x86.avx2.maskstore.d.
define <4 x i32> @test_x86_avx2_psllv_d(<4 x i32> %a0, <4 x i32> %a1) {
-; AVX2-LABEL: test_x86_avx2_psllv_d:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpsllvd %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x47,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_psllv_d:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpsllvd %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x47,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_psllv_d:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpsllvd %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x47,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_psllv_d:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpsllvd %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x47,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_psllv_d:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpsllvd %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x47,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_psllv_d:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpsllvd %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x47,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
ret <4 x i32> %res
}
@@ -1305,15 +1861,25 @@ declare <4 x i32> @llvm.x86.avx2.psllv.d
define <8 x i32> @test_x86_avx2_psllv_d_256(<8 x i32> %a0, <8 x i32> %a1) {
-; AVX2-LABEL: test_x86_avx2_psllv_d_256:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x47,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_psllv_d_256:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x47,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_psllv_d_256:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x47,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_psllv_d_256:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x47,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_psllv_d_256:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x47,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_psllv_d_256:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x47,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -1321,15 +1887,25 @@ declare <8 x i32> @llvm.x86.avx2.psllv.d
define <2 x i64> @test_x86_avx2_psllv_q(<2 x i64> %a0, <2 x i64> %a1) {
-; AVX2-LABEL: test_x86_avx2_psllv_q:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpsllvq %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0xf9,0x47,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_psllv_q:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpsllvq %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0xf9,0x47,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_psllv_q:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpsllvq %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0xf9,0x47,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_psllv_q:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpsllvq %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0xf9,0x47,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_psllv_q:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpsllvq %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0xf9,0x47,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_psllv_q:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpsllvq %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0xf9,0x47,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]
ret <2 x i64> %res
}
@@ -1337,15 +1913,25 @@ declare <2 x i64> @llvm.x86.avx2.psllv.q
define <4 x i64> @test_x86_avx2_psllv_q_256(<4 x i64> %a0, <4 x i64> %a1) {
-; AVX2-LABEL: test_x86_avx2_psllv_q_256:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpsllvq %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0xfd,0x47,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_psllv_q_256:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpsllvq %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0xfd,0x47,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_psllv_q_256:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpsllvq %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0xfd,0x47,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_psllv_q_256:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpsllvq %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0xfd,0x47,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_psllv_q_256:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpsllvq %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0xfd,0x47,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_psllv_q_256:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpsllvq %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0xfd,0x47,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> %a0, <4 x i64> %a1) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -1353,15 +1939,25 @@ declare <4 x i64> @llvm.x86.avx2.psllv.q
define <4 x i32> @test_x86_avx2_psrlv_d(<4 x i32> %a0, <4 x i32> %a1) {
-; AVX2-LABEL: test_x86_avx2_psrlv_d:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x45,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_psrlv_d:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x45,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_psrlv_d:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x45,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_psrlv_d:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x45,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_psrlv_d:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x45,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_psrlv_d:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x45,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
ret <4 x i32> %res
}
@@ -1369,15 +1965,25 @@ declare <4 x i32> @llvm.x86.avx2.psrlv.d
define <8 x i32> @test_x86_avx2_psrlv_d_256(<8 x i32> %a0, <8 x i32> %a1) {
-; AVX2-LABEL: test_x86_avx2_psrlv_d_256:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x45,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_psrlv_d_256:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x45,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_psrlv_d_256:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x45,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_psrlv_d_256:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x45,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_psrlv_d_256:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x45,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_psrlv_d_256:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x45,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -1385,15 +1991,25 @@ declare <8 x i32> @llvm.x86.avx2.psrlv.d
define <2 x i64> @test_x86_avx2_psrlv_q(<2 x i64> %a0, <2 x i64> %a1) {
-; AVX2-LABEL: test_x86_avx2_psrlv_q:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpsrlvq %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0xf9,0x45,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_psrlv_q:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpsrlvq %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0xf9,0x45,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_psrlv_q:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpsrlvq %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0xf9,0x45,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_psrlv_q:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpsrlvq %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0xf9,0x45,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_psrlv_q:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpsrlvq %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0xf9,0x45,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_psrlv_q:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpsrlvq %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0xf9,0x45,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]
ret <2 x i64> %res
}
@@ -1401,15 +2017,25 @@ declare <2 x i64> @llvm.x86.avx2.psrlv.q
define <4 x i64> @test_x86_avx2_psrlv_q_256(<4 x i64> %a0, <4 x i64> %a1) {
-; AVX2-LABEL: test_x86_avx2_psrlv_q_256:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpsrlvq %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0xfd,0x45,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_psrlv_q_256:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpsrlvq %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0xfd,0x45,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_psrlv_q_256:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpsrlvq %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0xfd,0x45,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_psrlv_q_256:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpsrlvq %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0xfd,0x45,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_psrlv_q_256:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpsrlvq %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0xfd,0x45,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_psrlv_q_256:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpsrlvq %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0xfd,0x45,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> %a0, <4 x i64> %a1) ; <<4 x i64>> [#uses=1]
ret <4 x i64> %res
}
@@ -1417,15 +2043,25 @@ declare <4 x i64> @llvm.x86.avx2.psrlv.q
define <4 x i32> @test_x86_avx2_psrav_d(<4 x i32> %a0, <4 x i32> %a1) {
-; AVX2-LABEL: test_x86_avx2_psrav_d:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpsravd %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x46,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_psrav_d:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpsravd %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x46,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_psrav_d:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpsravd %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x46,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_psrav_d:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpsravd %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x46,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_psrav_d:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpsravd %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x46,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_psrav_d:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpsravd %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x46,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
ret <4 x i32> %res
}
@@ -1435,52 +2071,62 @@ define <4 x i32> @test_x86_avx2_psrav_d_
; X86-AVX: ## %bb.0:
; X86-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [2,9,4294967284,23]
; X86-AVX-NEXT: ## encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; X86-AVX-NEXT: ## fixup A - offset: 4, value: LCPI88_0, kind: FK_Data_4
-; X86-AVX-NEXT: vpsravd LCPI88_1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A]
-; X86-AVX-NEXT: ## fixup A - offset: 5, value: LCPI88_1, kind: FK_Data_4
-; X86-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-NEXT: ## fixup A - offset: 4, value: LCPI86_0, kind: FK_Data_4
+; X86-AVX-NEXT: vpsravd LCPI86_1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A]
+; X86-AVX-NEXT: ## fixup A - offset: 5, value: LCPI86_1, kind: FK_Data_4
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
;
; X86-AVX512VL-LABEL: test_x86_avx2_psrav_d_const:
; X86-AVX512VL: ## %bb.0:
-; X86-AVX512VL-NEXT: vmovdqa LCPI88_0, %xmm0 ## EVEX TO VEX Compression xmm0 = [2,9,4294967284,23]
+; X86-AVX512VL-NEXT: vmovdqa LCPI86_0, %xmm0 ## EVEX TO VEX Compression xmm0 = [2,9,4294967284,23]
; X86-AVX512VL-NEXT: ## encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; X86-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI88_0, kind: FK_Data_4
-; X86-AVX512VL-NEXT: vpsravd LCPI88_1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A]
-; X86-AVX512VL-NEXT: ## fixup A - offset: 5, value: LCPI88_1, kind: FK_Data_4
-; X86-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI86_0, kind: FK_Data_4
+; X86-AVX512VL-NEXT: vpsravd LCPI86_1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A]
+; X86-AVX512VL-NEXT: ## fixup A - offset: 5, value: LCPI86_1, kind: FK_Data_4
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
;
; X64-AVX-LABEL: test_x86_avx2_psrav_d_const:
; X64-AVX: ## %bb.0:
; X64-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [2,9,4294967284,23]
; X64-AVX-NEXT: ## encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; X64-AVX-NEXT: ## fixup A - offset: 4, value: LCPI88_0-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: ## fixup A - offset: 4, value: LCPI86_0-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A]
-; X64-AVX-NEXT: ## fixup A - offset: 5, value: LCPI88_1-4, kind: reloc_riprel_4byte
-; X64-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-AVX-NEXT: ## fixup A - offset: 5, value: LCPI86_1-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
;
; X64-AVX512VL-LABEL: test_x86_avx2_psrav_d_const:
; X64-AVX512VL: ## %bb.0:
; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %xmm0 ## EVEX TO VEX Compression xmm0 = [2,9,4294967284,23]
; X64-AVX512VL-NEXT: ## encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
-; X64-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI88_0-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI86_0-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A]
-; X64-AVX512VL-NEXT: ## fixup A - offset: 5, value: LCPI88_1-4, kind: reloc_riprel_4byte
-; X64-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-AVX512VL-NEXT: ## fixup A - offset: 5, value: LCPI86_1-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> <i32 2, i32 9, i32 -12, i32 23>, <4 x i32> <i32 1, i32 18, i32 35, i32 52>)
ret <4 x i32> %res
}
declare <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32>, <4 x i32>) nounwind readnone
define <8 x i32> @test_x86_avx2_psrav_d_256(<8 x i32> %a0, <8 x i32> %a1) {
-; AVX2-LABEL: test_x86_avx2_psrav_d_256:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpsravd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x46,0xc1]
-; AVX2-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
-;
-; AVX512VL-LABEL: test_x86_avx2_psrav_d_256:
-; AVX512VL: ## %bb.0:
-; AVX512VL-NEXT: vpsravd %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x46,0xc1]
-; AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-LABEL: test_x86_avx2_psrav_d_256:
+; X86-AVX: ## %bb.0:
+; X86-AVX-NEXT: vpsravd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x46,0xc1]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
+;
+; X86-AVX512VL-LABEL: test_x86_avx2_psrav_d_256:
+; X86-AVX512VL: ## %bb.0:
+; X86-AVX512VL-NEXT: vpsravd %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x46,0xc1]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
+;
+; X64-AVX-LABEL: test_x86_avx2_psrav_d_256:
+; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: vpsravd %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x46,0xc1]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
+;
+; X64-AVX512VL-LABEL: test_x86_avx2_psrav_d_256:
+; X64-AVX512VL: ## %bb.0:
+; X64-AVX512VL-NEXT: vpsravd %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x46,0xc1]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
ret <8 x i32> %res
}
@@ -1490,37 +2136,37 @@ define <8 x i32> @test_x86_avx2_psrav_d_
; X86-AVX: ## %bb.0:
; X86-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
; X86-AVX-NEXT: ## encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
-; X86-AVX-NEXT: ## fixup A - offset: 4, value: LCPI90_0, kind: FK_Data_4
-; X86-AVX-NEXT: vpsravd LCPI90_1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
-; X86-AVX-NEXT: ## fixup A - offset: 5, value: LCPI90_1, kind: FK_Data_4
-; X86-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-NEXT: ## fixup A - offset: 4, value: LCPI88_0, kind: FK_Data_4
+; X86-AVX-NEXT: vpsravd LCPI88_1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
+; X86-AVX-NEXT: ## fixup A - offset: 5, value: LCPI88_1, kind: FK_Data_4
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
;
; X86-AVX512VL-LABEL: test_x86_avx2_psrav_d_256_const:
; X86-AVX512VL: ## %bb.0:
-; X86-AVX512VL-NEXT: vmovdqa LCPI90_0, %ymm0 ## EVEX TO VEX Compression ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
+; X86-AVX512VL-NEXT: vmovdqa LCPI88_0, %ymm0 ## EVEX TO VEX Compression ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
; X86-AVX512VL-NEXT: ## encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
-; X86-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI90_0, kind: FK_Data_4
-; X86-AVX512VL-NEXT: vpsravd LCPI90_1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
-; X86-AVX512VL-NEXT: ## fixup A - offset: 5, value: LCPI90_1, kind: FK_Data_4
-; X86-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI88_0, kind: FK_Data_4
+; X86-AVX512VL-NEXT: vpsravd LCPI88_1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
+; X86-AVX512VL-NEXT: ## fixup A - offset: 5, value: LCPI88_1, kind: FK_Data_4
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
;
; X64-AVX-LABEL: test_x86_avx2_psrav_d_256_const:
; X64-AVX: ## %bb.0:
; X64-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
; X64-AVX-NEXT: ## encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
-; X64-AVX-NEXT: ## fixup A - offset: 4, value: LCPI90_0-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: ## fixup A - offset: 4, value: LCPI88_0-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: vpsravd {{.*}}(%rip), %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
-; X64-AVX-NEXT: ## fixup A - offset: 5, value: LCPI90_1-4, kind: reloc_riprel_4byte
-; X64-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-AVX-NEXT: ## fixup A - offset: 5, value: LCPI88_1-4, kind: reloc_riprel_4byte
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
;
; X64-AVX512VL-LABEL: test_x86_avx2_psrav_d_256_const:
; X64-AVX512VL: ## %bb.0:
; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %ymm0 ## EVEX TO VEX Compression ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
; X64-AVX512VL-NEXT: ## encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
-; X64-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI90_0-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI88_0-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: vpsravd {{.*}}(%rip), %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
-; X64-AVX512VL-NEXT: ## fixup A - offset: 5, value: LCPI90_1-4, kind: reloc_riprel_4byte
-; X64-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-AVX512VL-NEXT: ## fixup A - offset: 5, value: LCPI88_1-4, kind: reloc_riprel_4byte
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> <i32 2, i32 9, i32 -12, i32 23, i32 -26, i32 37, i32 -40, i32 51>, <8 x i32> <i32 1, i32 18, i32 35, i32 52, i32 69, i32 15, i32 32, i32 49>)
ret <8 x i32> %res
}
@@ -1531,12 +2177,12 @@ define <2 x double> @test_x86_avx2_gathe
; X86: ## %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-NEXT: vgatherdpd %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0xe9,0x92,0x04,0x48]
-; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-NEXT: retl ## encoding: [0xc3]
;
; X64-LABEL: test_x86_avx2_gather_d_pd:
; X64: ## %bb.0:
; X64-NEXT: vgatherdpd %xmm2, (%rdi,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0xe9,0x92,0x04,0x4f]
-; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <2 x double> @llvm.x86.avx2.gather.d.pd(<2 x double> %a0,
i8* %a1, <4 x i32> %idx, <2 x double> %mask, i8 2) ;
ret <2 x double> %res
@@ -1549,12 +2195,12 @@ define <4 x double> @test_x86_avx2_gathe
; X86: ## %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-NEXT: vgatherdpd %ymm2, (%eax,%xmm1,2), %ymm0 ## encoding: [0xc4,0xe2,0xed,0x92,0x04,0x48]
-; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-NEXT: retl ## encoding: [0xc3]
;
; X64-LABEL: test_x86_avx2_gather_d_pd_256:
; X64: ## %bb.0:
; X64-NEXT: vgatherdpd %ymm2, (%rdi,%xmm1,2), %ymm0 ## encoding: [0xc4,0xe2,0xed,0x92,0x04,0x4f]
-; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <4 x double> @llvm.x86.avx2.gather.d.pd.256(<4 x double> %a0,
i8* %a1, <4 x i32> %idx, <4 x double> %mask, i8 2) ;
ret <4 x double> %res
@@ -1567,12 +2213,12 @@ define <2 x double> @test_x86_avx2_gathe
; X86: ## %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-NEXT: vgatherqpd %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0xe9,0x93,0x04,0x48]
-; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-NEXT: retl ## encoding: [0xc3]
;
; X64-LABEL: test_x86_avx2_gather_q_pd:
; X64: ## %bb.0:
; X64-NEXT: vgatherqpd %xmm2, (%rdi,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0xe9,0x93,0x04,0x4f]
-; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <2 x double> @llvm.x86.avx2.gather.q.pd(<2 x double> %a0,
i8* %a1, <2 x i64> %idx, <2 x double> %mask, i8 2) ;
ret <2 x double> %res
@@ -1585,12 +2231,12 @@ define <4 x double> @test_x86_avx2_gathe
; X86: ## %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-NEXT: vgatherqpd %ymm2, (%eax,%ymm1,2), %ymm0 ## encoding: [0xc4,0xe2,0xed,0x93,0x04,0x48]
-; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-NEXT: retl ## encoding: [0xc3]
;
; X64-LABEL: test_x86_avx2_gather_q_pd_256:
; X64: ## %bb.0:
; X64-NEXT: vgatherqpd %ymm2, (%rdi,%ymm1,2), %ymm0 ## encoding: [0xc4,0xe2,0xed,0x93,0x04,0x4f]
-; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <4 x double> @llvm.x86.avx2.gather.q.pd.256(<4 x double> %a0,
i8* %a1, <4 x i64> %idx, <4 x double> %mask, i8 2) ;
ret <4 x double> %res
@@ -1603,12 +2249,12 @@ define <4 x float> @test_x86_avx2_gather
; X86: ## %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-NEXT: vgatherdps %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x69,0x92,0x04,0x48]
-; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-NEXT: retl ## encoding: [0xc3]
;
; X64-LABEL: test_x86_avx2_gather_d_ps:
; X64: ## %bb.0:
; X64-NEXT: vgatherdps %xmm2, (%rdi,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x69,0x92,0x04,0x4f]
-; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <4 x float> @llvm.x86.avx2.gather.d.ps(<4 x float> %a0,
i8* %a1, <4 x i32> %idx, <4 x float> %mask, i8 2) ;
ret <4 x float> %res
@@ -1621,12 +2267,12 @@ define <8 x float> @test_x86_avx2_gather
; X86: ## %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-NEXT: vgatherdps %ymm2, (%eax,%ymm1,2), %ymm0 ## encoding: [0xc4,0xe2,0x6d,0x92,0x04,0x48]
-; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-NEXT: retl ## encoding: [0xc3]
;
; X64-LABEL: test_x86_avx2_gather_d_ps_256:
; X64: ## %bb.0:
; X64-NEXT: vgatherdps %ymm2, (%rdi,%ymm1,2), %ymm0 ## encoding: [0xc4,0xe2,0x6d,0x92,0x04,0x4f]
-; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> %a0,
i8* %a1, <8 x i32> %idx, <8 x float> %mask, i8 2) ;
ret <8 x float> %res
@@ -1639,12 +2285,12 @@ define <4 x float> @test_x86_avx2_gather
; X86: ## %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-NEXT: vgatherqps %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x69,0x93,0x04,0x48]
-; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-NEXT: retl ## encoding: [0xc3]
;
; X64-LABEL: test_x86_avx2_gather_q_ps:
; X64: ## %bb.0:
; X64-NEXT: vgatherqps %xmm2, (%rdi,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x69,0x93,0x04,0x4f]
-; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <4 x float> @llvm.x86.avx2.gather.q.ps(<4 x float> %a0,
i8* %a1, <2 x i64> %idx, <4 x float> %mask, i8 2) ;
ret <4 x float> %res
@@ -1658,13 +2304,13 @@ define <4 x float> @test_x86_avx2_gather
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-NEXT: vgatherqps %xmm2, (%eax,%ymm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x6d,0x93,0x04,0x48]
; X86-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
-; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-NEXT: retl ## encoding: [0xc3]
;
; X64-LABEL: test_x86_avx2_gather_q_ps_256:
; X64: ## %bb.0:
; X64-NEXT: vgatherqps %xmm2, (%rdi,%ymm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x6d,0x93,0x04,0x4f]
; X64-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
-; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <4 x float> @llvm.x86.avx2.gather.q.ps.256(<4 x float> %a0,
i8* %a1, <4 x i64> %idx, <4 x float> %mask, i8 2) ;
ret <4 x float> %res
@@ -1677,12 +2323,12 @@ define <2 x i64> @test_x86_avx2_gather_d
; X86: ## %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-NEXT: vpgatherdq %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0xe9,0x90,0x04,0x48]
-; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-NEXT: retl ## encoding: [0xc3]
;
; X64-LABEL: test_x86_avx2_gather_d_q:
; X64: ## %bb.0:
; X64-NEXT: vpgatherdq %xmm2, (%rdi,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0xe9,0x90,0x04,0x4f]
-; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <2 x i64> @llvm.x86.avx2.gather.d.q(<2 x i64> %a0,
i8* %a1, <4 x i32> %idx, <2 x i64> %mask, i8 2) ;
ret <2 x i64> %res
@@ -1695,12 +2341,12 @@ define <4 x i64> @test_x86_avx2_gather_d
; X86: ## %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-NEXT: vpgatherdq %ymm2, (%eax,%xmm1,2), %ymm0 ## encoding: [0xc4,0xe2,0xed,0x90,0x04,0x48]
-; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-NEXT: retl ## encoding: [0xc3]
;
; X64-LABEL: test_x86_avx2_gather_d_q_256:
; X64: ## %bb.0:
; X64-NEXT: vpgatherdq %ymm2, (%rdi,%xmm1,2), %ymm0 ## encoding: [0xc4,0xe2,0xed,0x90,0x04,0x4f]
-; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.gather.d.q.256(<4 x i64> %a0,
i8* %a1, <4 x i32> %idx, <4 x i64> %mask, i8 2) ;
ret <4 x i64> %res
@@ -1713,12 +2359,12 @@ define <2 x i64> @test_x86_avx2_gather_q
; X86: ## %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-NEXT: vpgatherqq %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0xe9,0x91,0x04,0x48]
-; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-NEXT: retl ## encoding: [0xc3]
;
; X64-LABEL: test_x86_avx2_gather_q_q:
; X64: ## %bb.0:
; X64-NEXT: vpgatherqq %xmm2, (%rdi,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0xe9,0x91,0x04,0x4f]
-; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <2 x i64> @llvm.x86.avx2.gather.q.q(<2 x i64> %a0,
i8* %a1, <2 x i64> %idx, <2 x i64> %mask, i8 2) ;
ret <2 x i64> %res
@@ -1731,12 +2377,12 @@ define <4 x i64> @test_x86_avx2_gather_q
; X86: ## %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-NEXT: vpgatherqq %ymm2, (%eax,%ymm1,2), %ymm0 ## encoding: [0xc4,0xe2,0xed,0x91,0x04,0x48]
-; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-NEXT: retl ## encoding: [0xc3]
;
; X64-LABEL: test_x86_avx2_gather_q_q_256:
; X64: ## %bb.0:
; X64-NEXT: vpgatherqq %ymm2, (%rdi,%ymm1,2), %ymm0 ## encoding: [0xc4,0xe2,0xed,0x91,0x04,0x4f]
-; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.gather.q.q.256(<4 x i64> %a0,
i8* %a1, <4 x i64> %idx, <4 x i64> %mask, i8 2) ;
ret <4 x i64> %res
@@ -1749,12 +2395,12 @@ define <4 x i32> @test_x86_avx2_gather_d
; X86: ## %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-NEXT: vpgatherdd %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x69,0x90,0x04,0x48]
-; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-NEXT: retl ## encoding: [0xc3]
;
; X64-LABEL: test_x86_avx2_gather_d_d:
; X64: ## %bb.0:
; X64-NEXT: vpgatherdd %xmm2, (%rdi,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x69,0x90,0x04,0x4f]
-; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <4 x i32> @llvm.x86.avx2.gather.d.d(<4 x i32> %a0,
i8* %a1, <4 x i32> %idx, <4 x i32> %mask, i8 2) ;
ret <4 x i32> %res
@@ -1767,12 +2413,12 @@ define <8 x i32> @test_x86_avx2_gather_d
; X86: ## %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-NEXT: vpgatherdd %ymm2, (%eax,%ymm1,2), %ymm0 ## encoding: [0xc4,0xe2,0x6d,0x90,0x04,0x48]
-; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-NEXT: retl ## encoding: [0xc3]
;
; X64-LABEL: test_x86_avx2_gather_d_d_256:
; X64: ## %bb.0:
; X64-NEXT: vpgatherdd %ymm2, (%rdi,%ymm1,2), %ymm0 ## encoding: [0xc4,0xe2,0x6d,0x90,0x04,0x4f]
-; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.gather.d.d.256(<8 x i32> %a0,
i8* %a1, <8 x i32> %idx, <8 x i32> %mask, i8 2) ;
ret <8 x i32> %res
@@ -1785,12 +2431,12 @@ define <4 x i32> @test_x86_avx2_gather_q
; X86: ## %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-NEXT: vpgatherqd %xmm2, (%eax,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x69,0x91,0x04,0x48]
-; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-NEXT: retl ## encoding: [0xc3]
;
; X64-LABEL: test_x86_avx2_gather_q_d:
; X64: ## %bb.0:
; X64-NEXT: vpgatherqd %xmm2, (%rdi,%xmm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x69,0x91,0x04,0x4f]
-; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <4 x i32> @llvm.x86.avx2.gather.q.d(<4 x i32> %a0,
i8* %a1, <2 x i64> %idx, <4 x i32> %mask, i8 2) ;
ret <4 x i32> %res
@@ -1804,13 +2450,13 @@ define <4 x i32> @test_x86_avx2_gather_q
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-NEXT: vpgatherqd %xmm2, (%eax,%ymm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x6d,0x91,0x04,0x48]
; X86-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
-; X86-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-NEXT: retl ## encoding: [0xc3]
;
; X64-LABEL: test_x86_avx2_gather_q_d_256:
; X64: ## %bb.0:
; X64-NEXT: vpgatherqd %xmm2, (%rdi,%ymm1,2), %xmm0 ## encoding: [0xc4,0xe2,0x6d,0x91,0x04,0x4f]
; X64-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
-; X64-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-NEXT: retq ## encoding: [0xc3]
%res = call <4 x i32> @llvm.x86.avx2.gather.q.d.256(<4 x i32> %a0,
i8* %a1, <4 x i64> %idx, <4 x i32> %mask, i8 2) ;
ret <4 x i32> %res
@@ -1828,7 +2474,7 @@ define <8 x float> @test_gather_mask(<8
; X86-AVX-NEXT: vmovaps %ymm2, %ymm3 ## encoding: [0xc5,0xfc,0x28,0xda]
; X86-AVX-NEXT: vgatherdps %ymm3, (%ecx,%ymm1,4), %ymm0 ## encoding: [0xc4,0xe2,0x65,0x92,0x04,0x89]
; X86-AVX-NEXT: vmovups %ymm2, (%eax) ## encoding: [0xc5,0xfc,0x11,0x10]
-; X86-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX-NEXT: retl ## encoding: [0xc3]
;
; X86-AVX512VL-LABEL: test_gather_mask:
; X86-AVX512VL: ## %bb.0:
@@ -1837,21 +2483,21 @@ define <8 x float> @test_gather_mask(<8
; X86-AVX512VL-NEXT: vmovaps %ymm2, %ymm3 ## EVEX TO VEX Compression encoding: [0xc5,0xfc,0x28,0xda]
; X86-AVX512VL-NEXT: vgatherdps %ymm3, (%ecx,%ymm1,4), %ymm0 ## encoding: [0xc4,0xe2,0x65,0x92,0x04,0x89]
; X86-AVX512VL-NEXT: vmovups %ymm2, (%eax) ## EVEX TO VEX Compression encoding: [0xc5,0xfc,0x11,0x10]
-; X86-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X86-AVX512VL-NEXT: retl ## encoding: [0xc3]
;
; X64-AVX-LABEL: test_gather_mask:
; X64-AVX: ## %bb.0:
; X64-AVX-NEXT: vmovaps %ymm2, %ymm3 ## encoding: [0xc5,0xfc,0x28,0xda]
; X64-AVX-NEXT: vgatherdps %ymm3, (%rdi,%ymm1,4), %ymm0 ## encoding: [0xc4,0xe2,0x65,0x92,0x04,0x8f]
; X64-AVX-NEXT: vmovups %ymm2, (%rsi) ## encoding: [0xc5,0xfc,0x11,0x16]
-; X64-AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-AVX-NEXT: retq ## encoding: [0xc3]
;
; X64-AVX512VL-LABEL: test_gather_mask:
; X64-AVX512VL: ## %bb.0:
; X64-AVX512VL-NEXT: vmovaps %ymm2, %ymm3 ## EVEX TO VEX Compression encoding: [0xc5,0xfc,0x28,0xda]
; X64-AVX512VL-NEXT: vgatherdps %ymm3, (%rdi,%ymm1,4), %ymm0 ## encoding: [0xc4,0xe2,0x65,0x92,0x04,0x8f]
; X64-AVX512VL-NEXT: vmovups %ymm2, (%rsi) ## EVEX TO VEX Compression encoding: [0xc5,0xfc,0x11,0x16]
-; X64-AVX512VL-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
+; X64-AVX512VL-NEXT: retq ## encoding: [0xc3]
%a_i8 = bitcast float* %a to i8*
%res = call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> %a0,
i8* %a_i8, <8 x i32> %idx, <8 x float> %mask, i8 4) ;
Modified: llvm/trunk/test/CodeGen/X86/avx512-intrinsics-upgrade.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-intrinsics-upgrade.ll?rev=329990&r1=329989&r2=329990&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-intrinsics-upgrade.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-intrinsics-upgrade.ll Thu Apr 12 23:07:18 2018
@@ -3882,3 +3882,241 @@ define i8 @test_cmppd(<8 x double> %a, <
ret i8 %res
}
declare i8 @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> , <8 x double> , i32, i8, i32)
+
+define <8 x i64> @test_mul_epi32_rr(<16 x i32> %a, <16 x i32> %b) {
+; CHECK-LABEL: test_mul_epi32_rr:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: vpmuldq %zmm1, %zmm0, %zmm0
+; CHECK-NEXT: retq
+ %res = call <8 x i64> @llvm.x86.avx512.pmul.dq.512(<16 x i32> %a, <16 x i32> %b)
+ ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mul_epi32_rrk(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask) {
+; CHECK-LABEL: test_mul_epi32_rrk:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %edi, %k1
+; CHECK-NEXT: vpmuldq %zmm1, %zmm0, %zmm2 {%k1}
+; CHECK-NEXT: vmovdqa64 %zmm2, %zmm0
+; CHECK-NEXT: retq
+ %mul = call <8 x i64> @llvm.x86.avx512.pmul.dq.512(<16 x i32> %a, <16 x i32> %b)
+ %mask.cast = bitcast i8 %mask to <8 x i1>
+ %res = select <8 x i1> %mask.cast, <8 x i64> %mul, <8 x i64> %passThru
+ ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mul_epi32_rrkz(<16 x i32> %a, <16 x i32> %b, i8 %mask) {
+; CHECK-LABEL: test_mul_epi32_rrkz:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %edi, %k1
+; CHECK-NEXT: vpmuldq %zmm1, %zmm0, %zmm0 {%k1} {z}
+; CHECK-NEXT: retq
+ %mul = call <8 x i64> @llvm.x86.avx512.pmul.dq.512(<16 x i32> %a, <16 x i32> %b)
+ %mask.cast = bitcast i8 %mask to <8 x i1>
+ %res = select <8 x i1> %mask.cast, <8 x i64> %mul, <8 x i64> zeroinitializer
+ ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mul_epi32_rm(<16 x i32> %a, <16 x i32>* %ptr_b) {
+; CHECK-LABEL: test_mul_epi32_rm:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: vpmuldq (%rdi), %zmm0, %zmm0
+; CHECK-NEXT: retq
+ %b = load <16 x i32>, <16 x i32>* %ptr_b
+ %res = call <8 x i64> @llvm.x86.avx512.pmul.dq.512(<16 x i32> %a, <16 x i32> %b)
+ ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mul_epi32_rmk(<16 x i32> %a, <16 x i32>* %ptr_b, <8 x i64> %passThru, i8 %mask) {
+; CHECK-LABEL: test_mul_epi32_rmk:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %esi, %k1
+; CHECK-NEXT: vpmuldq (%rdi), %zmm0, %zmm1 {%k1}
+; CHECK-NEXT: vmovdqa64 %zmm1, %zmm0
+; CHECK-NEXT: retq
+ %b = load <16 x i32>, <16 x i32>* %ptr_b
+ %mul = call <8 x i64> @llvm.x86.avx512.pmul.dq.512(<16 x i32> %a, <16 x i32> %b)
+ %mask.cast = bitcast i8 %mask to <8 x i1>
+ %res = select <8 x i1> %mask.cast, <8 x i64> %mul, <8 x i64> %passThru
+ ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mul_epi32_rmkz(<16 x i32> %a, <16 x i32>* %ptr_b, i8 %mask) {
+; CHECK-LABEL: test_mul_epi32_rmkz:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %esi, %k1
+; CHECK-NEXT: vpmuldq (%rdi), %zmm0, %zmm0 {%k1} {z}
+; CHECK-NEXT: retq
+ %b = load <16 x i32>, <16 x i32>* %ptr_b
+ %mul = call <8 x i64> @llvm.x86.avx512.pmul.dq.512(<16 x i32> %a, <16 x i32> %b)
+ %mask.cast = bitcast i8 %mask to <8 x i1>
+ %res = select <8 x i1> %mask.cast, <8 x i64> %mul, <8 x i64> zeroinitializer
+ ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mul_epi32_rmb(<16 x i32> %a, i64* %ptr_b) {
+; CHECK-LABEL: test_mul_epi32_rmb:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: vpmuldq (%rdi){1to8}, %zmm0, %zmm0
+; CHECK-NEXT: retq
+ %q = load i64, i64* %ptr_b
+ %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
+ %b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
+ %b = bitcast <8 x i64> %b64 to <16 x i32>
+ %res = call <8 x i64> @llvm.x86.avx512.pmul.dq.512(<16 x i32> %a, <16 x i32> %b)
+ ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mul_epi32_rmbk(<16 x i32> %a, i64* %ptr_b, <8 x i64> %passThru, i8 %mask) {
+; CHECK-LABEL: test_mul_epi32_rmbk:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %esi, %k1
+; CHECK-NEXT: vpmuldq (%rdi){1to8}, %zmm0, %zmm1 {%k1}
+; CHECK-NEXT: vmovdqa64 %zmm1, %zmm0
+; CHECK-NEXT: retq
+ %q = load i64, i64* %ptr_b
+ %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
+ %b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
+ %b = bitcast <8 x i64> %b64 to <16 x i32>
+ %mul = call <8 x i64> @llvm.x86.avx512.pmul.dq.512(<16 x i32> %a, <16 x i32> %b)
+ %mask.cast = bitcast i8 %mask to <8 x i1>
+ %res = select <8 x i1> %mask.cast, <8 x i64> %mul, <8 x i64> %passThru
+ ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mul_epi32_rmbkz(<16 x i32> %a, i64* %ptr_b, i8 %mask) {
+; CHECK-LABEL: test_mul_epi32_rmbkz:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %esi, %k1
+; CHECK-NEXT: vpmuldq (%rdi){1to8}, %zmm0, %zmm0 {%k1} {z}
+; CHECK-NEXT: retq
+ %q = load i64, i64* %ptr_b
+ %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
+ %b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
+ %b = bitcast <8 x i64> %b64 to <16 x i32>
+ %mul = call <8 x i64> @llvm.x86.avx512.pmul.dq.512(<16 x i32> %a, <16 x i32> %b)
+ %mask.cast = bitcast i8 %mask to <8 x i1>
+ %res = select <8 x i1> %mask.cast, <8 x i64> %mul, <8 x i64> zeroinitializer
+ ret < 8 x i64> %res
+}
+
+declare <8 x i64> @llvm.x86.avx512.pmul.dq.512(<16 x i32>, <16 x i32>)
+
+define <8 x i64> @test_mul_epu32_rr(<16 x i32> %a, <16 x i32> %b) {
+; CHECK-LABEL: test_mul_epu32_rr:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: vpmuludq %zmm1, %zmm0, %zmm0
+; CHECK-NEXT: retq
+ %res = call <8 x i64> @llvm.x86.avx512.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b)
+ ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mul_epu32_rrk(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask) {
+; CHECK-LABEL: test_mul_epu32_rrk:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %edi, %k1
+; CHECK-NEXT: vpmuludq %zmm1, %zmm0, %zmm2 {%k1}
+; CHECK-NEXT: vmovdqa64 %zmm2, %zmm0
+; CHECK-NEXT: retq
+ %mul = call <8 x i64> @llvm.x86.avx512.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b)
+ %mask.cast = bitcast i8 %mask to <8 x i1>
+ %res = select <8 x i1> %mask.cast, <8 x i64> %mul, <8 x i64> %passThru
+ ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mul_epu32_rrkz(<16 x i32> %a, <16 x i32> %b, i8 %mask) {
+; CHECK-LABEL: test_mul_epu32_rrkz:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %edi, %k1
+; CHECK-NEXT: vpmuludq %zmm1, %zmm0, %zmm0 {%k1} {z}
+; CHECK-NEXT: retq
+ %mul = call <8 x i64> @llvm.x86.avx512.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b)
+ %mask.cast = bitcast i8 %mask to <8 x i1>
+ %res = select <8 x i1> %mask.cast, <8 x i64> %mul, <8 x i64> zeroinitializer
+ ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mul_epu32_rm(<16 x i32> %a, <16 x i32>* %ptr_b) {
+; CHECK-LABEL: test_mul_epu32_rm:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: vpmuludq (%rdi), %zmm0, %zmm0
+; CHECK-NEXT: retq
+ %b = load <16 x i32>, <16 x i32>* %ptr_b
+ %res = call <8 x i64> @llvm.x86.avx512.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b)
+ ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mul_epu32_rmk(<16 x i32> %a, <16 x i32>* %ptr_b, <8 x i64> %passThru, i8 %mask) {
+; CHECK-LABEL: test_mul_epu32_rmk:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %esi, %k1
+; CHECK-NEXT: vpmuludq (%rdi), %zmm0, %zmm1 {%k1}
+; CHECK-NEXT: vmovdqa64 %zmm1, %zmm0
+; CHECK-NEXT: retq
+ %b = load <16 x i32>, <16 x i32>* %ptr_b
+ %mul = call <8 x i64> @llvm.x86.avx512.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b)
+ %mask.cast = bitcast i8 %mask to <8 x i1>
+ %res = select <8 x i1> %mask.cast, <8 x i64> %mul, <8 x i64> %passThru
+ ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mul_epu32_rmkz(<16 x i32> %a, <16 x i32>* %ptr_b, i8 %mask) {
+; CHECK-LABEL: test_mul_epu32_rmkz:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %esi, %k1
+; CHECK-NEXT: vpmuludq (%rdi), %zmm0, %zmm0 {%k1} {z}
+; CHECK-NEXT: retq
+ %b = load <16 x i32>, <16 x i32>* %ptr_b
+ %mul = call <8 x i64> @llvm.x86.avx512.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b)
+ %mask.cast = bitcast i8 %mask to <8 x i1>
+ %res = select <8 x i1> %mask.cast, <8 x i64> %mul, <8 x i64> zeroinitializer
+ ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mul_epu32_rmb(<16 x i32> %a, i64* %ptr_b) {
+; CHECK-LABEL: test_mul_epu32_rmb:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: vpmuludq (%rdi){1to8}, %zmm0, %zmm0
+; CHECK-NEXT: retq
+ %q = load i64, i64* %ptr_b
+ %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
+ %b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
+ %b = bitcast <8 x i64> %b64 to <16 x i32>
+ %res = call <8 x i64> @llvm.x86.avx512.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b)
+ ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mul_epu32_rmbk(<16 x i32> %a, i64* %ptr_b, <8 x i64> %passThru, i8 %mask) {
+; CHECK-LABEL: test_mul_epu32_rmbk:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %esi, %k1
+; CHECK-NEXT: vpmuludq (%rdi){1to8}, %zmm0, %zmm1 {%k1}
+; CHECK-NEXT: vmovdqa64 %zmm1, %zmm0
+; CHECK-NEXT: retq
+ %q = load i64, i64* %ptr_b
+ %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
+ %b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
+ %b = bitcast <8 x i64> %b64 to <16 x i32>
+ %mul = call <8 x i64> @llvm.x86.avx512.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b)
+ %mask.cast = bitcast i8 %mask to <8 x i1>
+ %res = select <8 x i1> %mask.cast, <8 x i64> %mul, <8 x i64> %passThru
+ ret < 8 x i64> %res
+}
+
+define <8 x i64> @test_mul_epu32_rmbkz(<16 x i32> %a, i64* %ptr_b, i8 %mask) {
+; CHECK-LABEL: test_mul_epu32_rmbkz:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %esi, %k1
+; CHECK-NEXT: vpmuludq (%rdi){1to8}, %zmm0, %zmm0 {%k1} {z}
+; CHECK-NEXT: retq
+ %q = load i64, i64* %ptr_b
+ %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
+ %b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
+ %b = bitcast <8 x i64> %b64 to <16 x i32>
+ %mul = call <8 x i64> @llvm.x86.avx512.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b)
+ %mask.cast = bitcast i8 %mask to <8 x i1>
+ %res = select <8 x i1> %mask.cast, <8 x i64> %mul, <8 x i64> zeroinitializer
+ ret < 8 x i64> %res
+}
+
+declare <8 x i64> @llvm.x86.avx512.pmulu.dq.512(<16 x i32>, <16 x i32>)
Modified: llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll?rev=329990&r1=329989&r2=329990&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll Thu Apr 12 23:07:18 2018
@@ -953,244 +953,6 @@ define <8 x double> @test_vmulpd_mask_rz
ret <8 x double> %res
}
-define <8 x i64> @test_mul_epi32_rr(<16 x i32> %a, <16 x i32> %b) {
-; CHECK-LABEL: test_mul_epi32_rr:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmuldq %zmm1, %zmm0, %zmm0
-; CHECK-NEXT: retq
- %res = call <8 x i64> @llvm.x86.avx512.pmul.dq.512(<16 x i32> %a, <16 x i32> %b)
- ret < 8 x i64> %res
-}
-
-define <8 x i64> @test_mul_epi32_rrk(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask) {
-; CHECK-LABEL: test_mul_epi32_rrk:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %edi, %k1
-; CHECK-NEXT: vpmuldq %zmm1, %zmm0, %zmm2 {%k1}
-; CHECK-NEXT: vmovdqa64 %zmm2, %zmm0
-; CHECK-NEXT: retq
- %mul = call <8 x i64> @llvm.x86.avx512.pmul.dq.512(<16 x i32> %a, <16 x i32> %b)
- %mask.cast = bitcast i8 %mask to <8 x i1>
- %res = select <8 x i1> %mask.cast, <8 x i64> %mul, <8 x i64> %passThru
- ret < 8 x i64> %res
-}
-
-define <8 x i64> @test_mul_epi32_rrkz(<16 x i32> %a, <16 x i32> %b, i8 %mask) {
-; CHECK-LABEL: test_mul_epi32_rrkz:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %edi, %k1
-; CHECK-NEXT: vpmuldq %zmm1, %zmm0, %zmm0 {%k1} {z}
-; CHECK-NEXT: retq
- %mul = call <8 x i64> @llvm.x86.avx512.pmul.dq.512(<16 x i32> %a, <16 x i32> %b)
- %mask.cast = bitcast i8 %mask to <8 x i1>
- %res = select <8 x i1> %mask.cast, <8 x i64> %mul, <8 x i64> zeroinitializer
- ret < 8 x i64> %res
-}
-
-define <8 x i64> @test_mul_epi32_rm(<16 x i32> %a, <16 x i32>* %ptr_b) {
-; CHECK-LABEL: test_mul_epi32_rm:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmuldq (%rdi), %zmm0, %zmm0
-; CHECK-NEXT: retq
- %b = load <16 x i32>, <16 x i32>* %ptr_b
- %res = call <8 x i64> @llvm.x86.avx512.pmul.dq.512(<16 x i32> %a, <16 x i32> %b)
- ret < 8 x i64> %res
-}
-
-define <8 x i64> @test_mul_epi32_rmk(<16 x i32> %a, <16 x i32>* %ptr_b, <8 x i64> %passThru, i8 %mask) {
-; CHECK-LABEL: test_mul_epi32_rmk:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %esi, %k1
-; CHECK-NEXT: vpmuldq (%rdi), %zmm0, %zmm1 {%k1}
-; CHECK-NEXT: vmovdqa64 %zmm1, %zmm0
-; CHECK-NEXT: retq
- %b = load <16 x i32>, <16 x i32>* %ptr_b
- %mul = call <8 x i64> @llvm.x86.avx512.pmul.dq.512(<16 x i32> %a, <16 x i32> %b)
- %mask.cast = bitcast i8 %mask to <8 x i1>
- %res = select <8 x i1> %mask.cast, <8 x i64> %mul, <8 x i64> %passThru
- ret < 8 x i64> %res
-}
-
-define <8 x i64> @test_mul_epi32_rmkz(<16 x i32> %a, <16 x i32>* %ptr_b, i8 %mask) {
-; CHECK-LABEL: test_mul_epi32_rmkz:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %esi, %k1
-; CHECK-NEXT: vpmuldq (%rdi), %zmm0, %zmm0 {%k1} {z}
-; CHECK-NEXT: retq
- %b = load <16 x i32>, <16 x i32>* %ptr_b
- %mul = call <8 x i64> @llvm.x86.avx512.pmul.dq.512(<16 x i32> %a, <16 x i32> %b)
- %mask.cast = bitcast i8 %mask to <8 x i1>
- %res = select <8 x i1> %mask.cast, <8 x i64> %mul, <8 x i64> zeroinitializer
- ret < 8 x i64> %res
-}
-
-define <8 x i64> @test_mul_epi32_rmb(<16 x i32> %a, i64* %ptr_b) {
-; CHECK-LABEL: test_mul_epi32_rmb:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmuldq (%rdi){1to8}, %zmm0, %zmm0
-; CHECK-NEXT: retq
- %q = load i64, i64* %ptr_b
- %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
- %b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
- %b = bitcast <8 x i64> %b64 to <16 x i32>
- %res = call <8 x i64> @llvm.x86.avx512.pmul.dq.512(<16 x i32> %a, <16 x i32> %b)
- ret < 8 x i64> %res
-}
-
-define <8 x i64> @test_mul_epi32_rmbk(<16 x i32> %a, i64* %ptr_b, <8 x i64> %passThru, i8 %mask) {
-; CHECK-LABEL: test_mul_epi32_rmbk:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %esi, %k1
-; CHECK-NEXT: vpmuldq (%rdi){1to8}, %zmm0, %zmm1 {%k1}
-; CHECK-NEXT: vmovdqa64 %zmm1, %zmm0
-; CHECK-NEXT: retq
- %q = load i64, i64* %ptr_b
- %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
- %b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
- %b = bitcast <8 x i64> %b64 to <16 x i32>
- %mul = call <8 x i64> @llvm.x86.avx512.pmul.dq.512(<16 x i32> %a, <16 x i32> %b)
- %mask.cast = bitcast i8 %mask to <8 x i1>
- %res = select <8 x i1> %mask.cast, <8 x i64> %mul, <8 x i64> %passThru
- ret < 8 x i64> %res
-}
-
-define <8 x i64> @test_mul_epi32_rmbkz(<16 x i32> %a, i64* %ptr_b, i8 %mask) {
-; CHECK-LABEL: test_mul_epi32_rmbkz:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %esi, %k1
-; CHECK-NEXT: vpmuldq (%rdi){1to8}, %zmm0, %zmm0 {%k1} {z}
-; CHECK-NEXT: retq
- %q = load i64, i64* %ptr_b
- %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
- %b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
- %b = bitcast <8 x i64> %b64 to <16 x i32>
- %mul = call <8 x i64> @llvm.x86.avx512.pmul.dq.512(<16 x i32> %a, <16 x i32> %b)
- %mask.cast = bitcast i8 %mask to <8 x i1>
- %res = select <8 x i1> %mask.cast, <8 x i64> %mul, <8 x i64> zeroinitializer
- ret < 8 x i64> %res
-}
-
-declare <8 x i64> @llvm.x86.avx512.pmul.dq.512(<16 x i32>, <16 x i32>)
-
-define <8 x i64> @test_mul_epu32_rr(<16 x i32> %a, <16 x i32> %b) {
-; CHECK-LABEL: test_mul_epu32_rr:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmuludq %zmm1, %zmm0, %zmm0
-; CHECK-NEXT: retq
- %res = call <8 x i64> @llvm.x86.avx512.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b)
- ret < 8 x i64> %res
-}
-
-define <8 x i64> @test_mul_epu32_rrk(<16 x i32> %a, <16 x i32> %b, <8 x i64> %passThru, i8 %mask) {
-; CHECK-LABEL: test_mul_epu32_rrk:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %edi, %k1
-; CHECK-NEXT: vpmuludq %zmm1, %zmm0, %zmm2 {%k1}
-; CHECK-NEXT: vmovdqa64 %zmm2, %zmm0
-; CHECK-NEXT: retq
- %mul = call <8 x i64> @llvm.x86.avx512.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b)
- %mask.cast = bitcast i8 %mask to <8 x i1>
- %res = select <8 x i1> %mask.cast, <8 x i64> %mul, <8 x i64> %passThru
- ret < 8 x i64> %res
-}
-
-define <8 x i64> @test_mul_epu32_rrkz(<16 x i32> %a, <16 x i32> %b, i8 %mask) {
-; CHECK-LABEL: test_mul_epu32_rrkz:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %edi, %k1
-; CHECK-NEXT: vpmuludq %zmm1, %zmm0, %zmm0 {%k1} {z}
-; CHECK-NEXT: retq
- %mul = call <8 x i64> @llvm.x86.avx512.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b)
- %mask.cast = bitcast i8 %mask to <8 x i1>
- %res = select <8 x i1> %mask.cast, <8 x i64> %mul, <8 x i64> zeroinitializer
- ret < 8 x i64> %res
-}
-
-define <8 x i64> @test_mul_epu32_rm(<16 x i32> %a, <16 x i32>* %ptr_b) {
-; CHECK-LABEL: test_mul_epu32_rm:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmuludq (%rdi), %zmm0, %zmm0
-; CHECK-NEXT: retq
- %b = load <16 x i32>, <16 x i32>* %ptr_b
- %res = call <8 x i64> @llvm.x86.avx512.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b)
- ret < 8 x i64> %res
-}
-
-define <8 x i64> @test_mul_epu32_rmk(<16 x i32> %a, <16 x i32>* %ptr_b, <8 x i64> %passThru, i8 %mask) {
-; CHECK-LABEL: test_mul_epu32_rmk:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %esi, %k1
-; CHECK-NEXT: vpmuludq (%rdi), %zmm0, %zmm1 {%k1}
-; CHECK-NEXT: vmovdqa64 %zmm1, %zmm0
-; CHECK-NEXT: retq
- %b = load <16 x i32>, <16 x i32>* %ptr_b
- %mul = call <8 x i64> @llvm.x86.avx512.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b)
- %mask.cast = bitcast i8 %mask to <8 x i1>
- %res = select <8 x i1> %mask.cast, <8 x i64> %mul, <8 x i64> %passThru
- ret < 8 x i64> %res
-}
-
-define <8 x i64> @test_mul_epu32_rmkz(<16 x i32> %a, <16 x i32>* %ptr_b, i8 %mask) {
-; CHECK-LABEL: test_mul_epu32_rmkz:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %esi, %k1
-; CHECK-NEXT: vpmuludq (%rdi), %zmm0, %zmm0 {%k1} {z}
-; CHECK-NEXT: retq
- %b = load <16 x i32>, <16 x i32>* %ptr_b
- %mul = call <8 x i64> @llvm.x86.avx512.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b)
- %mask.cast = bitcast i8 %mask to <8 x i1>
- %res = select <8 x i1> %mask.cast, <8 x i64> %mul, <8 x i64> zeroinitializer
- ret < 8 x i64> %res
-}
-
-define <8 x i64> @test_mul_epu32_rmb(<16 x i32> %a, i64* %ptr_b) {
-; CHECK-LABEL: test_mul_epu32_rmb:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmuludq (%rdi){1to8}, %zmm0, %zmm0
-; CHECK-NEXT: retq
- %q = load i64, i64* %ptr_b
- %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
- %b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
- %b = bitcast <8 x i64> %b64 to <16 x i32>
- %res = call <8 x i64> @llvm.x86.avx512.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b)
- ret < 8 x i64> %res
-}
-
-define <8 x i64> @test_mul_epu32_rmbk(<16 x i32> %a, i64* %ptr_b, <8 x i64> %passThru, i8 %mask) {
-; CHECK-LABEL: test_mul_epu32_rmbk:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %esi, %k1
-; CHECK-NEXT: vpmuludq (%rdi){1to8}, %zmm0, %zmm1 {%k1}
-; CHECK-NEXT: vmovdqa64 %zmm1, %zmm0
-; CHECK-NEXT: retq
- %q = load i64, i64* %ptr_b
- %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
- %b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
- %b = bitcast <8 x i64> %b64 to <16 x i32>
- %mul = call <8 x i64> @llvm.x86.avx512.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b)
- %mask.cast = bitcast i8 %mask to <8 x i1>
- %res = select <8 x i1> %mask.cast, <8 x i64> %mul, <8 x i64> %passThru
- ret < 8 x i64> %res
-}
-
-define <8 x i64> @test_mul_epu32_rmbkz(<16 x i32> %a, i64* %ptr_b, i8 %mask) {
-; CHECK-LABEL: test_mul_epu32_rmbkz:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %esi, %k1
-; CHECK-NEXT: vpmuludq (%rdi){1to8}, %zmm0, %zmm0 {%k1} {z}
-; CHECK-NEXT: retq
- %q = load i64, i64* %ptr_b
- %vecinit.i = insertelement <8 x i64> undef, i64 %q, i32 0
- %b64 = shufflevector <8 x i64> %vecinit.i, <8 x i64> undef, <8 x i32> zeroinitializer
- %b = bitcast <8 x i64> %b64 to <16 x i32>
- %mul = call <8 x i64> @llvm.x86.avx512.pmulu.dq.512(<16 x i32> %a, <16 x i32> %b)
- %mask.cast = bitcast i8 %mask to <8 x i1>
- %res = select <8 x i1> %mask.cast, <8 x i64> %mul, <8 x i64> zeroinitializer
- ret < 8 x i64> %res
-}
-
-declare <8 x i64> @llvm.x86.avx512.pmulu.dq.512(<16 x i32>, <16 x i32>)
-
define <16 x float> @test_mm512_maskz_add_round_ps_rn_sae(<16 x float> %a0, <16 x float> %a1, i16 %mask) {
; CHECK-LABEL: test_mm512_maskz_add_round_ps_rn_sae:
; CHECK: ## %bb.0:
Modified: llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll?rev=329990&r1=329989&r2=329990&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll Thu Apr 12 23:07:18 2018
@@ -6165,3 +6165,431 @@ define i8 @test_cmppd_128(<2 x double> %
ret i8 %res
}
declare i8 @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> , <2 x double> , i32, i8)
+
+define < 2 x i64> @test_mask_mul_epi32_rr_128(< 4 x i32> %a, < 4 x i32> %b) {
+; CHECK-LABEL: test_mask_mul_epi32_rr_128:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: vpmuldq %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x28,0xc1]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %res = call < 2 x i64> @llvm.x86.avx512.mask.pmul.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 -1)
+ ret < 2 x i64> %res
+}
+
+define < 2 x i64> @test_mask_mul_epi32_rrk_128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> %passThru, i8 %mask) {
+; CHECK-LABEL: test_mask_mul_epi32_rrk_128:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
+; CHECK-NEXT: vpmuldq %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf2,0xfd,0x09,0x28,0xd1]
+; CHECK-NEXT: vmovdqa %xmm2, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc2]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %res = call < 2 x i64> @llvm.x86.avx512.mask.pmul.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> %passThru, i8 %mask)
+ ret < 2 x i64> %res
+}
+
+define < 2 x i64> @test_mask_mul_epi32_rrkz_128(< 4 x i32> %a, < 4 x i32> %b, i8 %mask) {
+; CHECK-LABEL: test_mask_mul_epi32_rrkz_128:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
+; CHECK-NEXT: vpmuldq %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0x89,0x28,0xc1]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %res = call < 2 x i64> @llvm.x86.avx512.mask.pmul.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 %mask)
+ ret < 2 x i64> %res
+}
+
+define < 2 x i64> @test_mask_mul_epi32_rm_128(< 4 x i32> %a, < 4 x i32>* %ptr_b) {
+; CHECK-LABEL: test_mask_mul_epi32_rm_128:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: vpmuldq (%rdi), %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x28,0x07]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %b = load < 4 x i32>, < 4 x i32>* %ptr_b
+ %res = call < 2 x i64> @llvm.x86.avx512.mask.pmul.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 -1)
+ ret < 2 x i64> %res
+}
+
+define < 2 x i64> @test_mask_mul_epi32_rmk_128(< 4 x i32> %a, < 4 x i32>* %ptr_b, < 2 x i64> %passThru, i8 %mask) {
+; CHECK-LABEL: test_mask_mul_epi32_rmk_128:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
+; CHECK-NEXT: vpmuldq (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf2,0xfd,0x09,0x28,0x0f]
+; CHECK-NEXT: vmovdqa %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc1]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %b = load < 4 x i32>, < 4 x i32>* %ptr_b
+ %res = call < 2 x i64> @llvm.x86.avx512.mask.pmul.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> %passThru, i8 %mask)
+ ret < 2 x i64> %res
+}
+
+define < 2 x i64> @test_mask_mul_epi32_rmkz_128(< 4 x i32> %a, < 4 x i32>* %ptr_b, i8 %mask) {
+; CHECK-LABEL: test_mask_mul_epi32_rmkz_128:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
+; CHECK-NEXT: vpmuldq (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0x89,0x28,0x07]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %b = load < 4 x i32>, < 4 x i32>* %ptr_b
+ %res = call < 2 x i64> @llvm.x86.avx512.mask.pmul.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 %mask)
+ ret < 2 x i64> %res
+}
+
+define < 2 x i64> @test_mask_mul_epi32_rmb_128(< 4 x i32> %a, i64* %ptr_b) {
+; CHECK-LABEL: test_mask_mul_epi32_rmb_128:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: vpmuldq (%rdi){1to2}, %xmm0, %xmm0 ## encoding: [0x62,0xf2,0xfd,0x18,0x28,0x07]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %q = load i64, i64* %ptr_b
+ %vecinit.i = insertelement < 2 x i64> undef, i64 %q, i32 0
+ %b64 = shufflevector < 2 x i64> %vecinit.i, < 2 x i64> undef, <2 x i32> zeroinitializer
+ %b = bitcast < 2 x i64> %b64 to < 4 x i32>
+ %res = call < 2 x i64> @llvm.x86.avx512.mask.pmul.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 -1)
+ ret < 2 x i64> %res
+}
+
+define < 2 x i64> @test_mask_mul_epi32_rmbk_128(< 4 x i32> %a, i64* %ptr_b, < 2 x i64> %passThru, i8 %mask) {
+; CHECK-LABEL: test_mask_mul_epi32_rmbk_128:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
+; CHECK-NEXT: vpmuldq (%rdi){1to2}, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf2,0xfd,0x19,0x28,0x0f]
+; CHECK-NEXT: vmovdqa %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc1]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %q = load i64, i64* %ptr_b
+ %vecinit.i = insertelement < 2 x i64> undef, i64 %q, i32 0
+ %b64 = shufflevector < 2 x i64> %vecinit.i, < 2 x i64> undef, <2 x i32> zeroinitializer
+ %b = bitcast < 2 x i64> %b64 to < 4 x i32>
+ %res = call < 2 x i64> @llvm.x86.avx512.mask.pmul.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> %passThru, i8 %mask)
+ ret < 2 x i64> %res
+}
+
+define < 2 x i64> @test_mask_mul_epi32_rmbkz_128(< 4 x i32> %a, i64* %ptr_b, i8 %mask) {
+; CHECK-LABEL: test_mask_mul_epi32_rmbkz_128:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
+; CHECK-NEXT: vpmuldq (%rdi){1to2}, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0x99,0x28,0x07]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %q = load i64, i64* %ptr_b
+ %vecinit.i = insertelement < 2 x i64> undef, i64 %q, i32 0
+ %b64 = shufflevector < 2 x i64> %vecinit.i, < 2 x i64> undef, < 2 x i32> zeroinitializer
+ %b = bitcast < 2 x i64> %b64 to < 4 x i32>
+ %res = call < 2 x i64> @llvm.x86.avx512.mask.pmul.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 %mask)
+ ret < 2 x i64> %res
+}
+
+declare < 2 x i64> @llvm.x86.avx512.mask.pmul.dq.128(< 4 x i32>, < 4 x i32>, < 2 x i64>, i8)
+
+define < 4 x i64> @test_mask_mul_epi32_rr_256(< 8 x i32> %a, < 8 x i32> %b) {
+; CHECK-LABEL: test_mask_mul_epi32_rr_256:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: vpmuldq %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x28,0xc1]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %res = call < 4 x i64> @llvm.x86.avx512.mask.pmul.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 -1)
+ ret < 4 x i64> %res
+}
+
+define < 4 x i64> @test_mask_mul_epi32_rrk_256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> %passThru, i8 %mask) {
+; CHECK-LABEL: test_mask_mul_epi32_rrk_256:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
+; CHECK-NEXT: vpmuldq %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf2,0xfd,0x29,0x28,0xd1]
+; CHECK-NEXT: vmovdqa %ymm2, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0xc2]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %res = call < 4 x i64> @llvm.x86.avx512.mask.pmul.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> %passThru, i8 %mask)
+ ret < 4 x i64> %res
+}
+
+define < 4 x i64> @test_mask_mul_epi32_rrkz_256(< 8 x i32> %a, < 8 x i32> %b, i8 %mask) {
+; CHECK-LABEL: test_mask_mul_epi32_rrkz_256:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
+; CHECK-NEXT: vpmuldq %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0xa9,0x28,0xc1]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %res = call < 4 x i64> @llvm.x86.avx512.mask.pmul.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 %mask)
+ ret < 4 x i64> %res
+}
+
+define < 4 x i64> @test_mask_mul_epi32_rm_256(< 8 x i32> %a, < 8 x i32>* %ptr_b) {
+; CHECK-LABEL: test_mask_mul_epi32_rm_256:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: vpmuldq (%rdi), %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x28,0x07]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %b = load < 8 x i32>, < 8 x i32>* %ptr_b
+ %res = call < 4 x i64> @llvm.x86.avx512.mask.pmul.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 -1)
+ ret < 4 x i64> %res
+}
+
+define < 4 x i64> @test_mask_mul_epi32_rmk_256(< 8 x i32> %a, < 8 x i32>* %ptr_b, < 4 x i64> %passThru, i8 %mask) {
+; CHECK-LABEL: test_mask_mul_epi32_rmk_256:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
+; CHECK-NEXT: vpmuldq (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf2,0xfd,0x29,0x28,0x0f]
+; CHECK-NEXT: vmovdqa %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0xc1]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %b = load < 8 x i32>, < 8 x i32>* %ptr_b
+ %res = call < 4 x i64> @llvm.x86.avx512.mask.pmul.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> %passThru, i8 %mask)
+ ret < 4 x i64> %res
+}
+
+define < 4 x i64> @test_mask_mul_epi32_rmkz_256(< 8 x i32> %a, < 8 x i32>* %ptr_b, i8 %mask) {
+; CHECK-LABEL: test_mask_mul_epi32_rmkz_256:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
+; CHECK-NEXT: vpmuldq (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0xa9,0x28,0x07]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %b = load < 8 x i32>, < 8 x i32>* %ptr_b
+ %res = call < 4 x i64> @llvm.x86.avx512.mask.pmul.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 %mask)
+ ret < 4 x i64> %res
+}
+
+define < 4 x i64> @test_mask_mul_epi32_rmb_256(< 8 x i32> %a, i64* %ptr_b) {
+; CHECK-LABEL: test_mask_mul_epi32_rmb_256:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: vpmuldq (%rdi){1to4}, %ymm0, %ymm0 ## encoding: [0x62,0xf2,0xfd,0x38,0x28,0x07]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %q = load i64, i64* %ptr_b
+ %vecinit.i = insertelement < 4 x i64> undef, i64 %q, i32 0
+ %b64 = shufflevector < 4 x i64> %vecinit.i, < 4 x i64> undef, < 4 x i32> zeroinitializer
+ %b = bitcast < 4 x i64> %b64 to < 8 x i32>
+ %res = call < 4 x i64> @llvm.x86.avx512.mask.pmul.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 -1)
+ ret < 4 x i64> %res
+}
+
+define < 4 x i64> @test_mask_mul_epi32_rmbk_256(< 8 x i32> %a, i64* %ptr_b, < 4 x i64> %passThru, i8 %mask) {
+; CHECK-LABEL: test_mask_mul_epi32_rmbk_256:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
+; CHECK-NEXT: vpmuldq (%rdi){1to4}, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf2,0xfd,0x39,0x28,0x0f]
+; CHECK-NEXT: vmovdqa %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0xc1]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %q = load i64, i64* %ptr_b
+ %vecinit.i = insertelement < 4 x i64> undef, i64 %q, i32 0
+ %b64 = shufflevector < 4 x i64> %vecinit.i, < 4 x i64> undef, < 4 x i32> zeroinitializer
+ %b = bitcast < 4 x i64> %b64 to < 8 x i32>
+ %res = call < 4 x i64> @llvm.x86.avx512.mask.pmul.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> %passThru, i8 %mask)
+ ret < 4 x i64> %res
+}
+
+define < 4 x i64> @test_mask_mul_epi32_rmbkz_256(< 8 x i32> %a, i64* %ptr_b, i8 %mask) {
+; CHECK-LABEL: test_mask_mul_epi32_rmbkz_256:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
+; CHECK-NEXT: vpmuldq (%rdi){1to4}, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0xb9,0x28,0x07]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %q = load i64, i64* %ptr_b
+ %vecinit.i = insertelement < 4 x i64> undef, i64 %q, i32 0
+ %b64 = shufflevector < 4 x i64> %vecinit.i, < 4 x i64> undef, < 4 x i32> zeroinitializer
+ %b = bitcast < 4 x i64> %b64 to < 8 x i32>
+ %res = call < 4 x i64> @llvm.x86.avx512.mask.pmul.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 %mask)
+ ret < 4 x i64> %res
+}
+
+declare < 4 x i64> @llvm.x86.avx512.mask.pmul.dq.256(< 8 x i32>, < 8 x i32>, < 4 x i64>, i8)
+
+define < 2 x i64> @test_mask_mul_epu32_rr_128(< 4 x i32> %a, < 4 x i32> %b) {
+; CHECK-LABEL: test_mask_mul_epu32_rr_128:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: vpmuludq %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xf4,0xc1]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %res = call < 2 x i64> @llvm.x86.avx512.mask.pmulu.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 -1)
+ ret < 2 x i64> %res
+}
+
+define < 2 x i64> @test_mask_mul_epu32_rrk_128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> %passThru, i8 %mask) {
+; CHECK-LABEL: test_mask_mul_epu32_rrk_128:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
+; CHECK-NEXT: vpmuludq %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf1,0xfd,0x09,0xf4,0xd1]
+; CHECK-NEXT: vmovdqa %xmm2, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc2]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %res = call < 2 x i64> @llvm.x86.avx512.mask.pmulu.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> %passThru, i8 %mask)
+ ret < 2 x i64> %res
+}
+
+define < 2 x i64> @test_mask_mul_epu32_rrkz_128(< 4 x i32> %a, < 4 x i32> %b, i8 %mask) {
+; CHECK-LABEL: test_mask_mul_epu32_rrkz_128:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
+; CHECK-NEXT: vpmuludq %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0x89,0xf4,0xc1]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %res = call < 2 x i64> @llvm.x86.avx512.mask.pmulu.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 %mask)
+ ret < 2 x i64> %res
+}
+
+define < 2 x i64> @test_mask_mul_epu32_rm_128(< 4 x i32> %a, < 4 x i32>* %ptr_b) {
+; CHECK-LABEL: test_mask_mul_epu32_rm_128:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: vpmuludq (%rdi), %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xf4,0x07]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %b = load < 4 x i32>, < 4 x i32>* %ptr_b
+ %res = call < 2 x i64> @llvm.x86.avx512.mask.pmulu.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 -1)
+ ret < 2 x i64> %res
+}
+
+define < 2 x i64> @test_mask_mul_epu32_rmk_128(< 4 x i32> %a, < 4 x i32>* %ptr_b, < 2 x i64> %passThru, i8 %mask) {
+; CHECK-LABEL: test_mask_mul_epu32_rmk_128:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
+; CHECK-NEXT: vpmuludq (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x09,0xf4,0x0f]
+; CHECK-NEXT: vmovdqa %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc1]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %b = load < 4 x i32>, < 4 x i32>* %ptr_b
+ %res = call < 2 x i64> @llvm.x86.avx512.mask.pmulu.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> %passThru, i8 %mask)
+ ret < 2 x i64> %res
+}
+
+define < 2 x i64> @test_mask_mul_epu32_rmkz_128(< 4 x i32> %a, < 4 x i32>* %ptr_b, i8 %mask) {
+; CHECK-LABEL: test_mask_mul_epu32_rmkz_128:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
+; CHECK-NEXT: vpmuludq (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0x89,0xf4,0x07]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %b = load < 4 x i32>, < 4 x i32>* %ptr_b
+ %res = call < 2 x i64> @llvm.x86.avx512.mask.pmulu.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 %mask)
+ ret < 2 x i64> %res
+}
+
+define < 2 x i64> @test_mask_mul_epu32_rmb_128(< 4 x i32> %a, i64* %ptr_b) {
+; CHECK-LABEL: test_mask_mul_epu32_rmb_128:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: vpmuludq (%rdi){1to2}, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0xfd,0x18,0xf4,0x07]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %q = load i64, i64* %ptr_b
+ %vecinit.i = insertelement < 2 x i64> undef, i64 %q, i32 0
+ %b64 = shufflevector < 2 x i64> %vecinit.i, < 2 x i64> undef, <2 x i32> zeroinitializer
+ %b = bitcast < 2 x i64> %b64 to < 4 x i32>
+ %res = call < 2 x i64> @llvm.x86.avx512.mask.pmulu.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 -1)
+ ret < 2 x i64> %res
+}
+
+define < 2 x i64> @test_mask_mul_epu32_rmbk_128(< 4 x i32> %a, i64* %ptr_b, < 2 x i64> %passThru, i8 %mask) {
+; CHECK-LABEL: test_mask_mul_epu32_rmbk_128:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
+; CHECK-NEXT: vpmuludq (%rdi){1to2}, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x19,0xf4,0x0f]
+; CHECK-NEXT: vmovdqa %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc1]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %q = load i64, i64* %ptr_b
+ %vecinit.i = insertelement < 2 x i64> undef, i64 %q, i32 0
+ %b64 = shufflevector < 2 x i64> %vecinit.i, < 2 x i64> undef, <2 x i32> zeroinitializer
+ %b = bitcast < 2 x i64> %b64 to < 4 x i32>
+ %res = call < 2 x i64> @llvm.x86.avx512.mask.pmulu.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> %passThru, i8 %mask)
+ ret < 2 x i64> %res
+}
+
+define < 2 x i64> @test_mask_mul_epu32_rmbkz_128(< 4 x i32> %a, i64* %ptr_b, i8 %mask) {
+; CHECK-LABEL: test_mask_mul_epu32_rmbkz_128:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
+; CHECK-NEXT: vpmuludq (%rdi){1to2}, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0x99,0xf4,0x07]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %q = load i64, i64* %ptr_b
+ %vecinit.i = insertelement < 2 x i64> undef, i64 %q, i32 0
+ %b64 = shufflevector < 2 x i64> %vecinit.i, < 2 x i64> undef, < 2 x i32> zeroinitializer
+ %b = bitcast < 2 x i64> %b64 to < 4 x i32>
+ %res = call < 2 x i64> @llvm.x86.avx512.mask.pmulu.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 %mask)
+ ret < 2 x i64> %res
+}
+
+declare < 2 x i64> @llvm.x86.avx512.mask.pmulu.dq.128(< 4 x i32>, < 4 x i32>, < 2 x i64>, i8)
+
+define < 4 x i64> @test_mask_mul_epu32_rr_256(< 8 x i32> %a, < 8 x i32> %b) {
+; CHECK-LABEL: test_mask_mul_epu32_rr_256:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: vpmuludq %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf4,0xc1]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %res = call < 4 x i64> @llvm.x86.avx512.mask.pmulu.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 -1)
+ ret < 4 x i64> %res
+}
+
+define < 4 x i64> @test_mask_mul_epu32_rrk_256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> %passThru, i8 %mask) {
+; CHECK-LABEL: test_mask_mul_epu32_rrk_256:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
+; CHECK-NEXT: vpmuludq %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf1,0xfd,0x29,0xf4,0xd1]
+; CHECK-NEXT: vmovdqa %ymm2, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0xc2]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %res = call < 4 x i64> @llvm.x86.avx512.mask.pmulu.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> %passThru, i8 %mask)
+ ret < 4 x i64> %res
+}
+
+define < 4 x i64> @test_mask_mul_epu32_rrkz_256(< 8 x i32> %a, < 8 x i32> %b, i8 %mask) {
+; CHECK-LABEL: test_mask_mul_epu32_rrkz_256:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
+; CHECK-NEXT: vpmuludq %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xa9,0xf4,0xc1]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %res = call < 4 x i64> @llvm.x86.avx512.mask.pmulu.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 %mask)
+ ret < 4 x i64> %res
+}
+
+define < 4 x i64> @test_mask_mul_epu32_rm_256(< 8 x i32> %a, < 8 x i32>* %ptr_b) {
+; CHECK-LABEL: test_mask_mul_epu32_rm_256:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: vpmuludq (%rdi), %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf4,0x07]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %b = load < 8 x i32>, < 8 x i32>* %ptr_b
+ %res = call < 4 x i64> @llvm.x86.avx512.mask.pmulu.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 -1)
+ ret < 4 x i64> %res
+}
+
+define < 4 x i64> @test_mask_mul_epu32_rmk_256(< 8 x i32> %a, < 8 x i32>* %ptr_b, < 4 x i64> %passThru, i8 %mask) {
+; CHECK-LABEL: test_mask_mul_epu32_rmk_256:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
+; CHECK-NEXT: vpmuludq (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x29,0xf4,0x0f]
+; CHECK-NEXT: vmovdqa %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0xc1]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %b = load < 8 x i32>, < 8 x i32>* %ptr_b
+ %res = call < 4 x i64> @llvm.x86.avx512.mask.pmulu.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> %passThru, i8 %mask)
+ ret < 4 x i64> %res
+}
+
+define < 4 x i64> @test_mask_mul_epu32_rmkz_256(< 8 x i32> %a, < 8 x i32>* %ptr_b, i8 %mask) {
+; CHECK-LABEL: test_mask_mul_epu32_rmkz_256:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
+; CHECK-NEXT: vpmuludq (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xa9,0xf4,0x07]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %b = load < 8 x i32>, < 8 x i32>* %ptr_b
+ %res = call < 4 x i64> @llvm.x86.avx512.mask.pmulu.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 %mask)
+ ret < 4 x i64> %res
+}
+
+define < 4 x i64> @test_mask_mul_epu32_rmb_256(< 8 x i32> %a, i64* %ptr_b) {
+; CHECK-LABEL: test_mask_mul_epu32_rmb_256:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: vpmuludq (%rdi){1to4}, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0xfd,0x38,0xf4,0x07]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %q = load i64, i64* %ptr_b
+ %vecinit.i = insertelement < 4 x i64> undef, i64 %q, i32 0
+ %b64 = shufflevector < 4 x i64> %vecinit.i, < 4 x i64> undef, < 4 x i32> zeroinitializer
+ %b = bitcast < 4 x i64> %b64 to < 8 x i32>
+ %res = call < 4 x i64> @llvm.x86.avx512.mask.pmulu.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 -1)
+ ret < 4 x i64> %res
+}
+
+define < 4 x i64> @test_mask_mul_epu32_rmbk_256(< 8 x i32> %a, i64* %ptr_b, < 4 x i64> %passThru, i8 %mask) {
+; CHECK-LABEL: test_mask_mul_epu32_rmbk_256:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
+; CHECK-NEXT: vpmuludq (%rdi){1to4}, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x39,0xf4,0x0f]
+; CHECK-NEXT: vmovdqa %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0xc1]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %q = load i64, i64* %ptr_b
+ %vecinit.i = insertelement < 4 x i64> undef, i64 %q, i32 0
+ %b64 = shufflevector < 4 x i64> %vecinit.i, < 4 x i64> undef, < 4 x i32> zeroinitializer
+ %b = bitcast < 4 x i64> %b64 to < 8 x i32>
+ %res = call < 4 x i64> @llvm.x86.avx512.mask.pmulu.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> %passThru, i8 %mask)
+ ret < 4 x i64> %res
+}
+
+define < 4 x i64> @test_mask_mul_epu32_rmbkz_256(< 8 x i32> %a, i64* %ptr_b, i8 %mask) {
+; CHECK-LABEL: test_mask_mul_epu32_rmbkz_256:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
+; CHECK-NEXT: vpmuludq (%rdi){1to4}, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xb9,0xf4,0x07]
+; CHECK-NEXT: retq ## encoding: [0xc3]
+ %q = load i64, i64* %ptr_b
+ %vecinit.i = insertelement < 4 x i64> undef, i64 %q, i32 0
+ %b64 = shufflevector < 4 x i64> %vecinit.i, < 4 x i64> undef, < 4 x i32> zeroinitializer
+ %b = bitcast < 4 x i64> %b64 to < 8 x i32>
+ %res = call < 4 x i64> @llvm.x86.avx512.mask.pmulu.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 %mask)
+ ret < 4 x i64> %res
+}
+
+declare < 4 x i64> @llvm.x86.avx512.mask.pmulu.dq.256(< 8 x i32>, < 8 x i32>, < 4 x i64>, i8)
Modified: llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll?rev=329990&r1=329989&r2=329990&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll Thu Apr 12 23:07:18 2018
@@ -285,434 +285,6 @@ define <8 x i64> @expand12(i8* %addr, i8
declare <8 x i64> @llvm.x86.avx512.mask.expand.q.512(<8 x i64> , <8 x i64>, i8)
-define < 2 x i64> @test_mask_mul_epi32_rr_128(< 4 x i32> %a, < 4 x i32> %b) {
-; CHECK-LABEL: test_mask_mul_epi32_rr_128:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmuldq %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x28,0xc1]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %res = call < 2 x i64> @llvm.x86.avx512.mask.pmul.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 -1)
- ret < 2 x i64> %res
-}
-
-define < 2 x i64> @test_mask_mul_epi32_rrk_128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> %passThru, i8 %mask) {
-; CHECK-LABEL: test_mask_mul_epi32_rrk_128:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
-; CHECK-NEXT: vpmuldq %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf2,0xfd,0x09,0x28,0xd1]
-; CHECK-NEXT: vmovdqa %xmm2, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc2]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %res = call < 2 x i64> @llvm.x86.avx512.mask.pmul.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> %passThru, i8 %mask)
- ret < 2 x i64> %res
-}
-
-define < 2 x i64> @test_mask_mul_epi32_rrkz_128(< 4 x i32> %a, < 4 x i32> %b, i8 %mask) {
-; CHECK-LABEL: test_mask_mul_epi32_rrkz_128:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
-; CHECK-NEXT: vpmuldq %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0x89,0x28,0xc1]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %res = call < 2 x i64> @llvm.x86.avx512.mask.pmul.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 %mask)
- ret < 2 x i64> %res
-}
-
-define < 2 x i64> @test_mask_mul_epi32_rm_128(< 4 x i32> %a, < 4 x i32>* %ptr_b) {
-; CHECK-LABEL: test_mask_mul_epi32_rm_128:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmuldq (%rdi), %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x28,0x07]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %b = load < 4 x i32>, < 4 x i32>* %ptr_b
- %res = call < 2 x i64> @llvm.x86.avx512.mask.pmul.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 -1)
- ret < 2 x i64> %res
-}
-
-define < 2 x i64> @test_mask_mul_epi32_rmk_128(< 4 x i32> %a, < 4 x i32>* %ptr_b, < 2 x i64> %passThru, i8 %mask) {
-; CHECK-LABEL: test_mask_mul_epi32_rmk_128:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
-; CHECK-NEXT: vpmuldq (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf2,0xfd,0x09,0x28,0x0f]
-; CHECK-NEXT: vmovdqa %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc1]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %b = load < 4 x i32>, < 4 x i32>* %ptr_b
- %res = call < 2 x i64> @llvm.x86.avx512.mask.pmul.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> %passThru, i8 %mask)
- ret < 2 x i64> %res
-}
-
-define < 2 x i64> @test_mask_mul_epi32_rmkz_128(< 4 x i32> %a, < 4 x i32>* %ptr_b, i8 %mask) {
-; CHECK-LABEL: test_mask_mul_epi32_rmkz_128:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
-; CHECK-NEXT: vpmuldq (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0x89,0x28,0x07]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %b = load < 4 x i32>, < 4 x i32>* %ptr_b
- %res = call < 2 x i64> @llvm.x86.avx512.mask.pmul.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 %mask)
- ret < 2 x i64> %res
-}
-
-define < 2 x i64> @test_mask_mul_epi32_rmb_128(< 4 x i32> %a, i64* %ptr_b) {
-; CHECK-LABEL: test_mask_mul_epi32_rmb_128:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmuldq (%rdi){1to2}, %xmm0, %xmm0 ## encoding: [0x62,0xf2,0xfd,0x18,0x28,0x07]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %q = load i64, i64* %ptr_b
- %vecinit.i = insertelement < 2 x i64> undef, i64 %q, i32 0
- %b64 = shufflevector < 2 x i64> %vecinit.i, < 2 x i64> undef, <2 x i32> zeroinitializer
- %b = bitcast < 2 x i64> %b64 to < 4 x i32>
- %res = call < 2 x i64> @llvm.x86.avx512.mask.pmul.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 -1)
- ret < 2 x i64> %res
-}
-
-define < 2 x i64> @test_mask_mul_epi32_rmbk_128(< 4 x i32> %a, i64* %ptr_b, < 2 x i64> %passThru, i8 %mask) {
-; CHECK-LABEL: test_mask_mul_epi32_rmbk_128:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
-; CHECK-NEXT: vpmuldq (%rdi){1to2}, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf2,0xfd,0x19,0x28,0x0f]
-; CHECK-NEXT: vmovdqa %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc1]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %q = load i64, i64* %ptr_b
- %vecinit.i = insertelement < 2 x i64> undef, i64 %q, i32 0
- %b64 = shufflevector < 2 x i64> %vecinit.i, < 2 x i64> undef, <2 x i32> zeroinitializer
- %b = bitcast < 2 x i64> %b64 to < 4 x i32>
- %res = call < 2 x i64> @llvm.x86.avx512.mask.pmul.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> %passThru, i8 %mask)
- ret < 2 x i64> %res
-}
-
-define < 2 x i64> @test_mask_mul_epi32_rmbkz_128(< 4 x i32> %a, i64* %ptr_b, i8 %mask) {
-; CHECK-LABEL: test_mask_mul_epi32_rmbkz_128:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
-; CHECK-NEXT: vpmuldq (%rdi){1to2}, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0x99,0x28,0x07]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %q = load i64, i64* %ptr_b
- %vecinit.i = insertelement < 2 x i64> undef, i64 %q, i32 0
- %b64 = shufflevector < 2 x i64> %vecinit.i, < 2 x i64> undef, < 2 x i32> zeroinitializer
- %b = bitcast < 2 x i64> %b64 to < 4 x i32>
- %res = call < 2 x i64> @llvm.x86.avx512.mask.pmul.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 %mask)
- ret < 2 x i64> %res
-}
-
-declare < 2 x i64> @llvm.x86.avx512.mask.pmul.dq.128(< 4 x i32>, < 4 x i32>, < 2 x i64>, i8)
-
-define < 4 x i64> @test_mask_mul_epi32_rr_256(< 8 x i32> %a, < 8 x i32> %b) {
-; CHECK-LABEL: test_mask_mul_epi32_rr_256:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmuldq %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x28,0xc1]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %res = call < 4 x i64> @llvm.x86.avx512.mask.pmul.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 -1)
- ret < 4 x i64> %res
-}
-
-define < 4 x i64> @test_mask_mul_epi32_rrk_256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> %passThru, i8 %mask) {
-; CHECK-LABEL: test_mask_mul_epi32_rrk_256:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
-; CHECK-NEXT: vpmuldq %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf2,0xfd,0x29,0x28,0xd1]
-; CHECK-NEXT: vmovdqa %ymm2, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0xc2]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %res = call < 4 x i64> @llvm.x86.avx512.mask.pmul.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> %passThru, i8 %mask)
- ret < 4 x i64> %res
-}
-
-define < 4 x i64> @test_mask_mul_epi32_rrkz_256(< 8 x i32> %a, < 8 x i32> %b, i8 %mask) {
-; CHECK-LABEL: test_mask_mul_epi32_rrkz_256:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
-; CHECK-NEXT: vpmuldq %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0xa9,0x28,0xc1]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %res = call < 4 x i64> @llvm.x86.avx512.mask.pmul.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 %mask)
- ret < 4 x i64> %res
-}
-
-define < 4 x i64> @test_mask_mul_epi32_rm_256(< 8 x i32> %a, < 8 x i32>* %ptr_b) {
-; CHECK-LABEL: test_mask_mul_epi32_rm_256:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmuldq (%rdi), %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x28,0x07]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %b = load < 8 x i32>, < 8 x i32>* %ptr_b
- %res = call < 4 x i64> @llvm.x86.avx512.mask.pmul.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 -1)
- ret < 4 x i64> %res
-}
-
-define < 4 x i64> @test_mask_mul_epi32_rmk_256(< 8 x i32> %a, < 8 x i32>* %ptr_b, < 4 x i64> %passThru, i8 %mask) {
-; CHECK-LABEL: test_mask_mul_epi32_rmk_256:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
-; CHECK-NEXT: vpmuldq (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf2,0xfd,0x29,0x28,0x0f]
-; CHECK-NEXT: vmovdqa %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0xc1]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %b = load < 8 x i32>, < 8 x i32>* %ptr_b
- %res = call < 4 x i64> @llvm.x86.avx512.mask.pmul.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> %passThru, i8 %mask)
- ret < 4 x i64> %res
-}
-
-define < 4 x i64> @test_mask_mul_epi32_rmkz_256(< 8 x i32> %a, < 8 x i32>* %ptr_b, i8 %mask) {
-; CHECK-LABEL: test_mask_mul_epi32_rmkz_256:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
-; CHECK-NEXT: vpmuldq (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0xa9,0x28,0x07]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %b = load < 8 x i32>, < 8 x i32>* %ptr_b
- %res = call < 4 x i64> @llvm.x86.avx512.mask.pmul.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 %mask)
- ret < 4 x i64> %res
-}
-
-define < 4 x i64> @test_mask_mul_epi32_rmb_256(< 8 x i32> %a, i64* %ptr_b) {
-; CHECK-LABEL: test_mask_mul_epi32_rmb_256:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmuldq (%rdi){1to4}, %ymm0, %ymm0 ## encoding: [0x62,0xf2,0xfd,0x38,0x28,0x07]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %q = load i64, i64* %ptr_b
- %vecinit.i = insertelement < 4 x i64> undef, i64 %q, i32 0
- %b64 = shufflevector < 4 x i64> %vecinit.i, < 4 x i64> undef, < 4 x i32> zeroinitializer
- %b = bitcast < 4 x i64> %b64 to < 8 x i32>
- %res = call < 4 x i64> @llvm.x86.avx512.mask.pmul.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 -1)
- ret < 4 x i64> %res
-}
-
-define < 4 x i64> @test_mask_mul_epi32_rmbk_256(< 8 x i32> %a, i64* %ptr_b, < 4 x i64> %passThru, i8 %mask) {
-; CHECK-LABEL: test_mask_mul_epi32_rmbk_256:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
-; CHECK-NEXT: vpmuldq (%rdi){1to4}, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf2,0xfd,0x39,0x28,0x0f]
-; CHECK-NEXT: vmovdqa %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0xc1]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %q = load i64, i64* %ptr_b
- %vecinit.i = insertelement < 4 x i64> undef, i64 %q, i32 0
- %b64 = shufflevector < 4 x i64> %vecinit.i, < 4 x i64> undef, < 4 x i32> zeroinitializer
- %b = bitcast < 4 x i64> %b64 to < 8 x i32>
- %res = call < 4 x i64> @llvm.x86.avx512.mask.pmul.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> %passThru, i8 %mask)
- ret < 4 x i64> %res
-}
-
-define < 4 x i64> @test_mask_mul_epi32_rmbkz_256(< 8 x i32> %a, i64* %ptr_b, i8 %mask) {
-; CHECK-LABEL: test_mask_mul_epi32_rmbkz_256:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
-; CHECK-NEXT: vpmuldq (%rdi){1to4}, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf2,0xfd,0xb9,0x28,0x07]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %q = load i64, i64* %ptr_b
- %vecinit.i = insertelement < 4 x i64> undef, i64 %q, i32 0
- %b64 = shufflevector < 4 x i64> %vecinit.i, < 4 x i64> undef, < 4 x i32> zeroinitializer
- %b = bitcast < 4 x i64> %b64 to < 8 x i32>
- %res = call < 4 x i64> @llvm.x86.avx512.mask.pmul.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 %mask)
- ret < 4 x i64> %res
-}
-
-declare < 4 x i64> @llvm.x86.avx512.mask.pmul.dq.256(< 8 x i32>, < 8 x i32>, < 4 x i64>, i8)
-
-define < 2 x i64> @test_mask_mul_epu32_rr_128(< 4 x i32> %a, < 4 x i32> %b) {
-; CHECK-LABEL: test_mask_mul_epu32_rr_128:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmuludq %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xf4,0xc1]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %res = call < 2 x i64> @llvm.x86.avx512.mask.pmulu.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 -1)
- ret < 2 x i64> %res
-}
-
-define < 2 x i64> @test_mask_mul_epu32_rrk_128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> %passThru, i8 %mask) {
-; CHECK-LABEL: test_mask_mul_epu32_rrk_128:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
-; CHECK-NEXT: vpmuludq %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf1,0xfd,0x09,0xf4,0xd1]
-; CHECK-NEXT: vmovdqa %xmm2, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc2]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %res = call < 2 x i64> @llvm.x86.avx512.mask.pmulu.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> %passThru, i8 %mask)
- ret < 2 x i64> %res
-}
-
-define < 2 x i64> @test_mask_mul_epu32_rrkz_128(< 4 x i32> %a, < 4 x i32> %b, i8 %mask) {
-; CHECK-LABEL: test_mask_mul_epu32_rrkz_128:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
-; CHECK-NEXT: vpmuludq %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0x89,0xf4,0xc1]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %res = call < 2 x i64> @llvm.x86.avx512.mask.pmulu.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 %mask)
- ret < 2 x i64> %res
-}
-
-define < 2 x i64> @test_mask_mul_epu32_rm_128(< 4 x i32> %a, < 4 x i32>* %ptr_b) {
-; CHECK-LABEL: test_mask_mul_epu32_rm_128:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmuludq (%rdi), %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xf4,0x07]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %b = load < 4 x i32>, < 4 x i32>* %ptr_b
- %res = call < 2 x i64> @llvm.x86.avx512.mask.pmulu.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 -1)
- ret < 2 x i64> %res
-}
-
-define < 2 x i64> @test_mask_mul_epu32_rmk_128(< 4 x i32> %a, < 4 x i32>* %ptr_b, < 2 x i64> %passThru, i8 %mask) {
-; CHECK-LABEL: test_mask_mul_epu32_rmk_128:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
-; CHECK-NEXT: vpmuludq (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x09,0xf4,0x0f]
-; CHECK-NEXT: vmovdqa %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc1]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %b = load < 4 x i32>, < 4 x i32>* %ptr_b
- %res = call < 2 x i64> @llvm.x86.avx512.mask.pmulu.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> %passThru, i8 %mask)
- ret < 2 x i64> %res
-}
-
-define < 2 x i64> @test_mask_mul_epu32_rmkz_128(< 4 x i32> %a, < 4 x i32>* %ptr_b, i8 %mask) {
-; CHECK-LABEL: test_mask_mul_epu32_rmkz_128:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
-; CHECK-NEXT: vpmuludq (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0x89,0xf4,0x07]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %b = load < 4 x i32>, < 4 x i32>* %ptr_b
- %res = call < 2 x i64> @llvm.x86.avx512.mask.pmulu.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 %mask)
- ret < 2 x i64> %res
-}
-
-define < 2 x i64> @test_mask_mul_epu32_rmb_128(< 4 x i32> %a, i64* %ptr_b) {
-; CHECK-LABEL: test_mask_mul_epu32_rmb_128:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmuludq (%rdi){1to2}, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0xfd,0x18,0xf4,0x07]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %q = load i64, i64* %ptr_b
- %vecinit.i = insertelement < 2 x i64> undef, i64 %q, i32 0
- %b64 = shufflevector < 2 x i64> %vecinit.i, < 2 x i64> undef, <2 x i32> zeroinitializer
- %b = bitcast < 2 x i64> %b64 to < 4 x i32>
- %res = call < 2 x i64> @llvm.x86.avx512.mask.pmulu.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 -1)
- ret < 2 x i64> %res
-}
-
-define < 2 x i64> @test_mask_mul_epu32_rmbk_128(< 4 x i32> %a, i64* %ptr_b, < 2 x i64> %passThru, i8 %mask) {
-; CHECK-LABEL: test_mask_mul_epu32_rmbk_128:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
-; CHECK-NEXT: vpmuludq (%rdi){1to2}, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x19,0xf4,0x0f]
-; CHECK-NEXT: vmovdqa %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc1]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %q = load i64, i64* %ptr_b
- %vecinit.i = insertelement < 2 x i64> undef, i64 %q, i32 0
- %b64 = shufflevector < 2 x i64> %vecinit.i, < 2 x i64> undef, <2 x i32> zeroinitializer
- %b = bitcast < 2 x i64> %b64 to < 4 x i32>
- %res = call < 2 x i64> @llvm.x86.avx512.mask.pmulu.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> %passThru, i8 %mask)
- ret < 2 x i64> %res
-}
-
-define < 2 x i64> @test_mask_mul_epu32_rmbkz_128(< 4 x i32> %a, i64* %ptr_b, i8 %mask) {
-; CHECK-LABEL: test_mask_mul_epu32_rmbkz_128:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
-; CHECK-NEXT: vpmuludq (%rdi){1to2}, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0x99,0xf4,0x07]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %q = load i64, i64* %ptr_b
- %vecinit.i = insertelement < 2 x i64> undef, i64 %q, i32 0
- %b64 = shufflevector < 2 x i64> %vecinit.i, < 2 x i64> undef, < 2 x i32> zeroinitializer
- %b = bitcast < 2 x i64> %b64 to < 4 x i32>
- %res = call < 2 x i64> @llvm.x86.avx512.mask.pmulu.dq.128(< 4 x i32> %a, < 4 x i32> %b, < 2 x i64> zeroinitializer, i8 %mask)
- ret < 2 x i64> %res
-}
-
-declare < 2 x i64> @llvm.x86.avx512.mask.pmulu.dq.128(< 4 x i32>, < 4 x i32>, < 2 x i64>, i8)
-
-define < 4 x i64> @test_mask_mul_epu32_rr_256(< 8 x i32> %a, < 8 x i32> %b) {
-; CHECK-LABEL: test_mask_mul_epu32_rr_256:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmuludq %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf4,0xc1]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %res = call < 4 x i64> @llvm.x86.avx512.mask.pmulu.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 -1)
- ret < 4 x i64> %res
-}
-
-define < 4 x i64> @test_mask_mul_epu32_rrk_256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> %passThru, i8 %mask) {
-; CHECK-LABEL: test_mask_mul_epu32_rrk_256:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
-; CHECK-NEXT: vpmuludq %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf1,0xfd,0x29,0xf4,0xd1]
-; CHECK-NEXT: vmovdqa %ymm2, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0xc2]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %res = call < 4 x i64> @llvm.x86.avx512.mask.pmulu.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> %passThru, i8 %mask)
- ret < 4 x i64> %res
-}
-
-define < 4 x i64> @test_mask_mul_epu32_rrkz_256(< 8 x i32> %a, < 8 x i32> %b, i8 %mask) {
-; CHECK-LABEL: test_mask_mul_epu32_rrkz_256:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
-; CHECK-NEXT: vpmuludq %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xa9,0xf4,0xc1]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %res = call < 4 x i64> @llvm.x86.avx512.mask.pmulu.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 %mask)
- ret < 4 x i64> %res
-}
-
-define < 4 x i64> @test_mask_mul_epu32_rm_256(< 8 x i32> %a, < 8 x i32>* %ptr_b) {
-; CHECK-LABEL: test_mask_mul_epu32_rm_256:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmuludq (%rdi), %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xf4,0x07]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %b = load < 8 x i32>, < 8 x i32>* %ptr_b
- %res = call < 4 x i64> @llvm.x86.avx512.mask.pmulu.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 -1)
- ret < 4 x i64> %res
-}
-
-define < 4 x i64> @test_mask_mul_epu32_rmk_256(< 8 x i32> %a, < 8 x i32>* %ptr_b, < 4 x i64> %passThru, i8 %mask) {
-; CHECK-LABEL: test_mask_mul_epu32_rmk_256:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
-; CHECK-NEXT: vpmuludq (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x29,0xf4,0x0f]
-; CHECK-NEXT: vmovdqa %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0xc1]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %b = load < 8 x i32>, < 8 x i32>* %ptr_b
- %res = call < 4 x i64> @llvm.x86.avx512.mask.pmulu.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> %passThru, i8 %mask)
- ret < 4 x i64> %res
-}
-
-define < 4 x i64> @test_mask_mul_epu32_rmkz_256(< 8 x i32> %a, < 8 x i32>* %ptr_b, i8 %mask) {
-; CHECK-LABEL: test_mask_mul_epu32_rmkz_256:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
-; CHECK-NEXT: vpmuludq (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xa9,0xf4,0x07]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %b = load < 8 x i32>, < 8 x i32>* %ptr_b
- %res = call < 4 x i64> @llvm.x86.avx512.mask.pmulu.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 %mask)
- ret < 4 x i64> %res
-}
-
-define < 4 x i64> @test_mask_mul_epu32_rmb_256(< 8 x i32> %a, i64* %ptr_b) {
-; CHECK-LABEL: test_mask_mul_epu32_rmb_256:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: vpmuludq (%rdi){1to4}, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0xfd,0x38,0xf4,0x07]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %q = load i64, i64* %ptr_b
- %vecinit.i = insertelement < 4 x i64> undef, i64 %q, i32 0
- %b64 = shufflevector < 4 x i64> %vecinit.i, < 4 x i64> undef, < 4 x i32> zeroinitializer
- %b = bitcast < 4 x i64> %b64 to < 8 x i32>
- %res = call < 4 x i64> @llvm.x86.avx512.mask.pmulu.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 -1)
- ret < 4 x i64> %res
-}
-
-define < 4 x i64> @test_mask_mul_epu32_rmbk_256(< 8 x i32> %a, i64* %ptr_b, < 4 x i64> %passThru, i8 %mask) {
-; CHECK-LABEL: test_mask_mul_epu32_rmbk_256:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
-; CHECK-NEXT: vpmuludq (%rdi){1to4}, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x39,0xf4,0x0f]
-; CHECK-NEXT: vmovdqa %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0xc1]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %q = load i64, i64* %ptr_b
- %vecinit.i = insertelement < 4 x i64> undef, i64 %q, i32 0
- %b64 = shufflevector < 4 x i64> %vecinit.i, < 4 x i64> undef, < 4 x i32> zeroinitializer
- %b = bitcast < 4 x i64> %b64 to < 8 x i32>
- %res = call < 4 x i64> @llvm.x86.avx512.mask.pmulu.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> %passThru, i8 %mask)
- ret < 4 x i64> %res
-}
-
-define < 4 x i64> @test_mask_mul_epu32_rmbkz_256(< 8 x i32> %a, i64* %ptr_b, i8 %mask) {
-; CHECK-LABEL: test_mask_mul_epu32_rmbkz_256:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
-; CHECK-NEXT: vpmuludq (%rdi){1to4}, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xb9,0xf4,0x07]
-; CHECK-NEXT: retq ## encoding: [0xc3]
- %q = load i64, i64* %ptr_b
- %vecinit.i = insertelement < 4 x i64> undef, i64 %q, i32 0
- %b64 = shufflevector < 4 x i64> %vecinit.i, < 4 x i64> undef, < 4 x i32> zeroinitializer
- %b = bitcast < 4 x i64> %b64 to < 8 x i32>
- %res = call < 4 x i64> @llvm.x86.avx512.mask.pmulu.dq.256(< 8 x i32> %a, < 8 x i32> %b, < 4 x i64> zeroinitializer, i8 %mask)
- ret < 4 x i64> %res
-}
-
-declare < 4 x i64> @llvm.x86.avx512.mask.pmulu.dq.256(< 8 x i32>, < 8 x i32>, < 4 x i64>, i8)
-
define i8 @test_cmpps_256(<8 x float> %a, <8 x float> %b) {
; CHECK-LABEL: test_cmpps_256:
; CHECK: ## %bb.0:
Modified: llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll?rev=329990&r1=329989&r2=329990&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll Thu Apr 12 23:07:18 2018
@@ -247,3 +247,12 @@ define <8 x i16> @mm_avg_epu16(<8 x i16>
declare <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16>, <8 x i16>) nounwind readnone
+define <2 x i64> @test_x86_sse2_pmulu_dq(<4 x i32> %a0, <4 x i32> %a1) {
+; CHECK-LABEL: test_x86_sse2_pmulu_dq:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: pmuludq %xmm1, %xmm0
+; CHECK-NEXT: retl
+ %res = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> %a0, <4 x i32> %a1) ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %res
+}
+declare <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32>, <4 x i32>) nounwind readnone
Modified: llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll?rev=329990&r1=329989&r2=329990&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll Thu Apr 12 23:07:18 2018
@@ -1129,27 +1129,6 @@ define <8 x i16> @test_x86_sse2_pmulhu_w
declare <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16>, <8 x i16>) nounwind readnone
-define <2 x i64> @test_x86_sse2_pmulu_dq(<4 x i32> %a0, <4 x i32> %a1) {
-; SSE-LABEL: test_x86_sse2_pmulu_dq:
-; SSE: ## %bb.0:
-; SSE-NEXT: pmuludq %xmm1, %xmm0 ## encoding: [0x66,0x0f,0xf4,0xc1]
-; SSE-NEXT: retl ## encoding: [0xc3]
-;
-; AVX2-LABEL: test_x86_sse2_pmulu_dq:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpmuludq %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xf4,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
-;
-; SKX-LABEL: test_x86_sse2_pmulu_dq:
-; SKX: ## %bb.0:
-; SKX-NEXT: vpmuludq %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xf4,0xc1]
-; SKX-NEXT: retl ## encoding: [0xc3]
- %res = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> %a0, <4 x i32> %a1) ; <<2 x i64>> [#uses=1]
- ret <2 x i64> %res
-}
-declare <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32>, <4 x i32>) nounwind readnone
-
-
define <2 x i64> @test_x86_sse2_psad_bw(<16 x i8> %a0, <16 x i8> %a1) {
; SSE-LABEL: test_x86_sse2_psad_bw:
; SSE: ## %bb.0:
Modified: llvm/trunk/test/CodeGen/X86/sse41-intrinsics-fast-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse41-intrinsics-fast-isel.ll?rev=329990&r1=329989&r2=329990&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse41-intrinsics-fast-isel.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse41-intrinsics-fast-isel.ll Thu Apr 12 23:07:18 2018
@@ -817,7 +817,6 @@ define <2 x i64> @test_mm_mul_epi32(<2 x
%res = mul nsw <2 x i64> %A1, %B1
ret <2 x i64> %res
}
-declare <2 x i64> @llvm.x86.sse41.pmuldq(<4 x i32>, <4 x i32>) nounwind readnone
define <2 x i64> @test_mm_mullo_epi32(<2 x i64> %a0, <2 x i64> %a1) {
; X32-LABEL: test_mm_mullo_epi32:
Modified: llvm/trunk/test/CodeGen/X86/sse41-intrinsics-x86-upgrade.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse41-intrinsics-x86-upgrade.ll?rev=329990&r1=329989&r2=329990&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse41-intrinsics-x86-upgrade.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse41-intrinsics-x86-upgrade.ll Thu Apr 12 23:07:18 2018
@@ -305,3 +305,13 @@ define <4 x i32> @min_epu32(<4 x i32> %a
}
declare <4 x i32> @llvm.x86.sse41.pminud(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <2 x i64> @test_x86_sse41_pmuldq(<4 x i32> %a0, <4 x i32> %a1) {
+; CHECK-LABEL: test_x86_sse41_pmuldq:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: pmuldq %xmm1, %xmm0
+; CHECK-NEXT: retl
+ %res = call <2 x i64> @llvm.x86.sse41.pmuldq(<4 x i32> %a0, <4 x i32> %a1) ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %res
+}
+declare <2 x i64> @llvm.x86.sse41.pmuldq(<4 x i32>, <4 x i32>) nounwind readnone
Modified: llvm/trunk/test/CodeGen/X86/sse41-intrinsics-x86.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse41-intrinsics-x86.ll?rev=329990&r1=329989&r2=329990&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse41-intrinsics-x86.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse41-intrinsics-x86.ll Thu Apr 12 23:07:18 2018
@@ -364,27 +364,6 @@ define <8 x i16> @test_x86_sse41_pminuw(
declare <8 x i16> @llvm.x86.sse41.pminuw(<8 x i16>, <8 x i16>) nounwind readnone
-define <2 x i64> @test_x86_sse41_pmuldq(<4 x i32> %a0, <4 x i32> %a1) {
-; SSE41-LABEL: test_x86_sse41_pmuldq:
-; SSE41: ## %bb.0:
-; SSE41-NEXT: pmuldq %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x38,0x28,0xc1]
-; SSE41-NEXT: retl ## encoding: [0xc3]
-;
-; AVX2-LABEL: test_x86_sse41_pmuldq:
-; AVX2: ## %bb.0:
-; AVX2-NEXT: vpmuldq %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x28,0xc1]
-; AVX2-NEXT: retl ## encoding: [0xc3]
-;
-; SKX-LABEL: test_x86_sse41_pmuldq:
-; SKX: ## %bb.0:
-; SKX-NEXT: vpmuldq %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x28,0xc1]
-; SKX-NEXT: retl ## encoding: [0xc3]
- %res = call <2 x i64> @llvm.x86.sse41.pmuldq(<4 x i32> %a0, <4 x i32> %a1) ; <<2 x i64>> [#uses=1]
- ret <2 x i64> %res
-}
-declare <2 x i64> @llvm.x86.sse41.pmuldq(<4 x i32>, <4 x i32>) nounwind readnone
-
-
define i32 @test_x86_sse41_ptestc(<2 x i64> %a0, <2 x i64> %a1) {
; SSE41-LABEL: test_x86_sse41_ptestc:
; SSE41: ## %bb.0:
Modified: llvm/trunk/test/Transforms/InstCombine/X86/x86-muldq.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/X86/x86-muldq.ll?rev=329990&r1=329989&r2=329990&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/X86/x86-muldq.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/X86/x86-muldq.ll Thu Apr 12 23:07:18 2018
@@ -159,10 +159,15 @@ define <8 x i64> @fold_pmuldq_512(<16 x
define <2 x i64> @test_demanded_elts_pmuludq_128(<4 x i32> %a0, <4 x i32> %a1) {
; CHECK-LABEL: @test_demanded_elts_pmuludq_128(
-; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> %a1, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
-; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> %a0, <4 x i32> [[TMP1]])
-; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i64> [[TMP2]], <2 x i64> undef, <2 x i32> zeroinitializer
-; CHECK-NEXT: ret <2 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[A0:%.*]], <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 undef, i32 undef>
+; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[A1:%.*]], <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 undef, i32 undef>
+; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to <2 x i64>
+; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to <2 x i64>
+; CHECK-NEXT: [[TMP5:%.*]] = and <2 x i64> [[TMP3]], <i64 4294967295, i64 undef>
+; CHECK-NEXT: [[TMP6:%.*]] = and <2 x i64> [[TMP4]], <i64 4294967295, i64 undef>
+; CHECK-NEXT: [[TMP7:%.*]] = mul nuw <2 x i64> [[TMP5]], [[TMP6]]
+; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x i64> [[TMP7]], <2 x i64> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT: ret <2 x i64> [[TMP8]]
;
%1 = shufflevector <4 x i32> %a0, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
%2 = shufflevector <4 x i32> %a1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
@@ -173,9 +178,14 @@ define <2 x i64> @test_demanded_elts_pmu
define <4 x i64> @test_demanded_elts_pmuludq_256(<8 x i32> %a0, <8 x i32> %a1) {
; CHECK-LABEL: @test_demanded_elts_pmuludq_256(
-; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> %a1, <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 3, i32 undef, i32 5, i32 undef, i32 7, i32 undef>
-; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i64> @llvm.x86.avx2.pmulu.dq(<8 x i32> %a0, <8 x i32> [[TMP1]])
-; CHECK-NEXT: ret <4 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A0:%.*]], <8 x i32> undef, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6>
+; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[A1:%.*]], <8 x i32> undef, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7>
+; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i32> [[TMP1]] to <4 x i64>
+; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP2]] to <4 x i64>
+; CHECK-NEXT: [[TMP5:%.*]] = and <4 x i64> [[TMP3]], <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
+; CHECK-NEXT: [[TMP6:%.*]] = and <4 x i64> [[TMP4]], <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
+; CHECK-NEXT: [[TMP7:%.*]] = mul nuw <4 x i64> [[TMP5]], [[TMP6]]
+; CHECK-NEXT: ret <4 x i64> [[TMP7]]
;
%1 = shufflevector <8 x i32> %a0, <8 x i32> undef, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6>
%2 = shufflevector <8 x i32> %a1, <8 x i32> undef, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7>
@@ -185,9 +195,14 @@ define <4 x i64> @test_demanded_elts_pmu
define <8 x i64> @test_demanded_elts_pmuludq_512(<16 x i32> %a0, <16 x i32> %a1) {
; CHECK-LABEL: @test_demanded_elts_pmuludq_512(
-; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> %a1, <16 x i32> undef, <16 x i32> <i32 1, i32 undef, i32 3, i32 undef, i32 5, i32 undef, i32 7, i32 undef, i32 9, i32 undef, i32 11, i32 undef, i32 13, i32 undef, i32 15, i32 undef>
-; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i64> @llvm.x86.avx512.pmulu.dq.512(<16 x i32> %a0, <16 x i32> [[TMP1]])
-; CHECK-NEXT: ret <8 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[A0:%.*]], <16 x i32> undef, <16 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6, i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14>
+; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x i32> [[A1:%.*]], <16 x i32> undef, <16 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7, i32 9, i32 9, i32 11, i32 11, i32 13, i32 13, i32 15, i32 15>
+; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to <8 x i64>
+; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to <8 x i64>
+; CHECK-NEXT: [[TMP5:%.*]] = and <8 x i64> [[TMP3]], <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
+; CHECK-NEXT: [[TMP6:%.*]] = and <8 x i64> [[TMP4]], <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
+; CHECK-NEXT: [[TMP7:%.*]] = mul nuw <8 x i64> [[TMP5]], [[TMP6]]
+; CHECK-NEXT: ret <8 x i64> [[TMP7]]
;
%1 = shufflevector <16 x i32> %a0, <16 x i32> undef, <16 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6, i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14>
%2 = shufflevector <16 x i32> %a1, <16 x i32> undef, <16 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7, i32 9, i32 9, i32 11, i32 11, i32 13, i32 13, i32 15, i32 15>
@@ -197,9 +212,16 @@ define <8 x i64> @test_demanded_elts_pmu
define <2 x i64> @test_demanded_elts_pmuldq_128(<4 x i32> %a0, <4 x i32> %a1) {
; CHECK-LABEL: @test_demanded_elts_pmuldq_128(
-; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> %a1, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 3, i32 undef>
-; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i64> @llvm.x86.sse41.pmuldq(<4 x i32> %a0, <4 x i32> [[TMP1]])
-; CHECK-NEXT: ret <2 x i64> [[TMP2]]
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[A0:%.*]], <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
+; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[A1:%.*]], <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
+; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to <2 x i64>
+; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to <2 x i64>
+; CHECK-NEXT: [[TMP5:%.*]] = shl <2 x i64> [[TMP3]], <i64 32, i64 32>
+; CHECK-NEXT: [[TMP6:%.*]] = ashr exact <2 x i64> [[TMP5]], <i64 32, i64 32>
+; CHECK-NEXT: [[TMP7:%.*]] = shl <2 x i64> [[TMP4]], <i64 32, i64 32>
+; CHECK-NEXT: [[TMP8:%.*]] = ashr exact <2 x i64> [[TMP7]], <i64 32, i64 32>
+; CHECK-NEXT: [[TMP9:%.*]] = mul nsw <2 x i64> [[TMP6]], [[TMP8]]
+; CHECK-NEXT: ret <2 x i64> [[TMP9]]
;
%1 = shufflevector <4 x i32> %a0, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
%2 = shufflevector <4 x i32> %a1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
@@ -209,10 +231,17 @@ define <2 x i64> @test_demanded_elts_pmu
define <4 x i64> @test_demanded_elts_pmuldq_256(<8 x i32> %a0, <8 x i32> %a1) {
; CHECK-LABEL: @test_demanded_elts_pmuldq_256(
-; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> %a1, <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 7, i32 undef>
-; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i64> @llvm.x86.avx2.pmul.dq(<8 x i32> %a0, <8 x i32> [[TMP1]])
-; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i64> [[TMP2]], <4 x i64> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3>
-; CHECK-NEXT: ret <4 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A0:%.*]], <8 x i32> undef, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6>
+; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[A1:%.*]], <8 x i32> undef, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7>
+; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i32> [[TMP1]] to <4 x i64>
+; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP2]] to <4 x i64>
+; CHECK-NEXT: [[TMP5:%.*]] = shl <4 x i64> [[TMP3]], <i64 32, i64 32, i64 32, i64 32>
+; CHECK-NEXT: [[TMP6:%.*]] = ashr exact <4 x i64> [[TMP5]], <i64 32, i64 32, i64 32, i64 32>
+; CHECK-NEXT: [[TMP7:%.*]] = shl <4 x i64> [[TMP4]], <i64 32, i64 32, i64 32, i64 32>
+; CHECK-NEXT: [[TMP8:%.*]] = ashr exact <4 x i64> [[TMP7]], <i64 32, i64 32, i64 32, i64 32>
+; CHECK-NEXT: [[TMP9:%.*]] = mul nsw <4 x i64> [[TMP6]], [[TMP8]]
+; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <4 x i64> [[TMP9]], <4 x i64> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3>
+; CHECK-NEXT: ret <4 x i64> [[TMP10]]
;
%1 = shufflevector <8 x i32> %a0, <8 x i32> undef, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6>
%2 = shufflevector <8 x i32> %a1, <8 x i32> undef, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7>
@@ -223,10 +252,17 @@ define <4 x i64> @test_demanded_elts_pmu
define <8 x i64> @test_demanded_elts_pmuldq_512(<16 x i32> %a0, <16 x i32> %a1) {
; CHECK-LABEL: @test_demanded_elts_pmuldq_512(
-; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> %a1, <16 x i32> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 7, i32 undef, i32 9, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 15, i32 undef>
-; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i64> @llvm.x86.avx512.pmul.dq.512(<16 x i32> %a0, <16 x i32> [[TMP1]])
-; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i64> [[TMP2]], <8 x i64> undef, <8 x i32> <i32 0, i32 0, i32 3, i32 3, i32 4, i32 4, i32 7, i32 7>
-; CHECK-NEXT: ret <8 x i64> [[TMP3]]
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[A0:%.*]], <16 x i32> undef, <16 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6, i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14>
+; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x i32> [[A1:%.*]], <16 x i32> undef, <16 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7, i32 9, i32 9, i32 11, i32 11, i32 13, i32 13, i32 15, i32 15>
+; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to <8 x i64>
+; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to <8 x i64>
+; CHECK-NEXT: [[TMP5:%.*]] = shl <8 x i64> [[TMP3]], <i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32>
+; CHECK-NEXT: [[TMP6:%.*]] = ashr exact <8 x i64> [[TMP5]], <i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32>
+; CHECK-NEXT: [[TMP7:%.*]] = shl <8 x i64> [[TMP4]], <i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32>
+; CHECK-NEXT: [[TMP8:%.*]] = ashr exact <8 x i64> [[TMP7]], <i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32>
+; CHECK-NEXT: [[TMP9:%.*]] = mul nsw <8 x i64> [[TMP6]], [[TMP8]]
+; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <8 x i64> [[TMP9]], <8 x i64> undef, <8 x i32> <i32 0, i32 0, i32 3, i32 3, i32 4, i32 4, i32 7, i32 7>
+; CHECK-NEXT: ret <8 x i64> [[TMP10]]
;
%1 = shufflevector <16 x i32> %a0, <16 x i32> undef, <16 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6, i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14>
%2 = shufflevector <16 x i32> %a1, <16 x i32> undef, <16 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7, i32 9, i32 9, i32 11, i32 11, i32 13, i32 13, i32 15, i32 15>
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